I am using XILINX ZC702 FPGA with Vivado 2014.3 along with SDK (software development kit).
I want to create FIFO data stream, which is not less than 20 i.e. under flow and not higher than 500 i.e. over flow. I have used AXI4 Stream FIFO IP for this purpose, in order to make the code work, I have to use registers which can be find in the datasheet for the axi stream fifo pasted below.
If the FIFO data reaches 500, then it should stop loading new data, If the FIFO data reaches 20, then it should fill new data until it gets to 500. This process should repeat all the time.
I made a test procedural in software development kit for fifo, in order to see the simulated waveform results through hardware. What I observe is that the FIFO data is not continuous. I need to have it in continuous mode, it should never stop, It should be like a loop.
Below please find the c code
#include <stdio.h>
#include <xil_types.h>
#include <xil_cache.h>
#include "platform.h"
#include "xil_io.h"
//#include "usb20_per.h"
int main()
{
#define SLCR_UNLOCK 0xF8000008
#define SLCR_UNLOCK_VAL 0xDF0D
#define SLCR_LOCK 0xF8000004
#define SLCR_LOCK_VAL 0x767B
#define XSLCR_FPGA_RST_CTRL 0xF8000240
uint32_t baseaddr_ber=0x43c00000;
uint32_t baseaddr_fifo=0x43c10000;
Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL); //
Xil_Out32(XSLCR_FPGA_RST_CTRL, 0x0000000F); //Reset FPGAx_OUT_RST
Xil_Out32(XSLCR_FPGA_RST_CTRL, 0x00000000); //Deassert the FPGAx_OUT_RST
Xil_Out32(SLCR_LOCK, SLCR_LOCK_VAL); //
Xil_ICacheEnable();
Xil_DCacheEnable();
print("---Entering main---\n\r");
init_platform();
// Xil_Out32 & Xil_In32
Xil_Out32(baseaddr_fifo+0x4, 0x0C0001FC); //IER //interrupt enable register
Xil_Out32(baseaddr_fifo+0x2C,0x00000002); //TDR //transmit data register
uint32_t word_cnt;
uint32_t idx;
uint32_t state;
uint32_t i,val;
#define ARRAY_LENGTH 16
uint32_t array_fifo_data[ARRAY_LENGTH] = { 0x0100, 0x0302, 0x0504, 0x0706, 0x0908, 0x0B0A, 0x0D0C, 0x0F0E, 0x0100, 0x0302, 0x0504, 0x0706, 0x0908, 0x0B0A, 0x0D0C, 0x0F0E }; //random sequence
state=0;
word_cnt=0;
idx=0;
while(1)
{
switch (state)
{
case 0:
val = Xil_In32(baseaddr_fifo + 0x0c);
if(val > 0x1A0) //check TDFV register value //transmit data fifo vacancy
{
state++;
}
else
{
val=0;
}
break;
case 1:
word_cnt=0;
for(i=0;i<16;i++)
{
Xil_Out32(baseaddr_fifo + 0x10, array_fifo_data[idx]); //Fill TXFIFO_DATA if TDFV falls below 20 and above 500
word_cnt++;
idx++;
if (idx>(ARRAY_LENGTH-1))
idx=0;
}
Xil_Out32(baseaddr_fifo+0x14,word_cnt*4); //TLR (transmit length register)
state=0;
break;
}
}
}
Below, there is a link for the datasheet of axi strem fifo IP. Page # 7, trasnmit a packet and Page # 23, register space shows the baseaddress and offset address of the registers I have been using in the code above.
I would really appreciate your help.
From the code I made, I can see the FIFO working and transmitting the sequential random data I put in the code, but the process is not continuous, it stops after transfering the data, it should repeat the process and keep on continuing it, it should never stop, like a loop.
Kinly open the link below to see the simulated waveform results. You will see that the fifo works, it transmits the complete random requence and after that it stops, I am expecting to repeatedly transmit the random sequence.
https://www.dropbox.com/sh/nydws0v5yjyphj3/AAAg_l7aEvUG3gEzhYedwgWra?dl=0
