Verilog(modelsim) language error when compiling

Question

hi i am getting a Cannot determine language of C:/Modeltech_pe_edu_10.3c/examples error when i try to compile this verilog code. It seems pretty simplistic to me. Am doing something wrong? Any suggestions would be helpful. I don't like Modelsim but were forced to use it. I'm curious if there is an issue with the settings or something.

This implements a basic ALU design using a case statement. Please help. I will try on Xilinx a little later to see if i can run it. Thank you!

`timescale 1ns / 1ps

module alu(result,operand0,operand1,control)
    (
        input   [31:0]  operand0, 
        input   [31:0]  operand1, 
        input   [3:0]   control,

        output  [31:0]  result,
        reg     [31:0]  result;

    always @(control, operand0, operand1)
    begin
      case(control)
      4'b0000: result = operand0 && operand1;
      4'b0001: result = operand0 || operand1;
      4'b0010: result = operand0 ^ operand1;
      4'b0011: result = operand0 ~| operand1;
      4'b0100: result = operand0 + operand1;
      4'b0110: result = operand0 - operand1;
      4'b1000: result = operand0 < operand1;
      4'b1001: result = operand0 << operand1;
      4'b1010: result = operand0 >> operand1;
      4'b1011: result = operand0 >>> operand1;
      endcase
    end

endmodule

You should add the command you execute and the exact error message from modelsim to your question, to make it easier for people to give you a good answer. — sebs

Greg Greg · Accepted Answer · 2014-11-08T00:45:46

Look like you mixed ANSI and non-ANSI styles. This would all simulators

non-ANSI (IEEE Std 1364-1995 and up):

module alu(result,operand0,operand1,control)
// ( <-- you have an open parenthesizes that should be here
    input   [31:0]  operand0;
    input   [31:0]  operand1; 
    input   [3:0]   control;

    output  [31:0]  result;
    reg     [31:0]  result;

or ANSI (IEEE Std 1364-2001 and up):

module alu(
    output reg [31:0]  result,
    input      [31:0]  operand0, operand1, 
    input       [3:0]  control
  );

Other recommendation: Use always @* for an auto sencitivity list instead of always @(control, operand0, operand1). If you need to follow IEEE Std 1364-1995 then use always @(control or operand0 or operand1) as the , feature for sensitively list (as well as @*) was added in IEEE Std 1364-2001.

Verilog(modelsim) language error when compiling

1 Answers