VHDL: slowing clock down methods

Question

as a newbie to VHDL I wondered if there was any particular reason why I cannot slow my clock down using counters alone? In all the examples I looked at so far, people seem to have created an entity and separate process for the new clock. The code below is my attempt.

variable clk_counter : integer range 0 to 30 := 0;
begin
if rising_edge(clk) then
 clk_counter:=clk_counter+1;
   if clk_counter = 30 then
    clk_counter := 0;
    ...

Any help would be much appreciated.

Is the code in your question one of the examples you're referring to, or your attempt to simplify them? — fru1tbat
1. It's personal preference if you want to create a whole new entity or not. 2. Realize that you are not "slowing down" the clock. You are creating a counter that acts as a clock_enable. When clk_counter=30, you can allow some code to execute. But all of your code should be clocked at the same frequency, your main clk. — Russell
The code is my attempt. Russel, the trouble I'm having is that I'd expect the counter to clock_enable once every 30 clock cycles. But, it doesn't seem to register on the rest of my code — BayK
Assuming that the things you want to happen all occur inside the if clk_counter = 30 then statement, this should successfully clock enable once every 30 cycles. There are some important differences between clock enables and clock division though. First of all, using a clock enable this way will not affect your actual clock signal at all, it only affects the registers inside of your if statement. Secondly, if you do complex logic, you will still be limited by the setup and hold time of your original clock. Using an actual clock divider will relax your setup and hold times. — QuantumRipple
The problem with using an actual clock divider however, is that it is more complex to do. While it is possible to use a toggle based on a counter as a clock, it will have very poor timing performance as the internal nets are not optimized for minimal skew like dedicated clock nets. Therefore dividing clock buffer primitives or MMCM/PLLs are used to create a new slower (or faster) clock. — QuantumRipple

chris chris · Accepted Answer · 2014-12-09T00:43:43

A bit late, but here is a simple way to achieve clock scaling. Change the length of the scaling vector to whatever you need. Pass clockScalers(x) as the scaled clock.

signal clockScalers : std_logic_vector(30 downto 0);
-- Clock process 
process (clk100mhz, rst) begin
    if (rst = '1') then
        clockScalers <= (others=>'0');

    elsif (clk100mhz'event and clk100mhz = '1') then
        clockScalers <= clockScalers + '1';
    end if; 
end process;

VHDL: slowing clock down methods

1 Answers