Verilog counter counts wrong

Question

I'm trying to implement a counter that counts up an internal value every clock-pulse with an input value.

module Counter(in, clk, out);

   input clk;
   input [7:0] in;

   wire clk;
   wire [7:0]  in;

   output [7:0] out;

   reg [7:0]    out;

   always @ (posedge clk) begin
      out <= out + in;
   end

endmodule

The output I get is correct most of the time but sometimes the counter does not increment as expected. Here is a link to a waveform of the output. As can be seen the counter jumps from 5 to 10 even though in is 3. Can someone help me?

Tim Tim · Accepted Answer · 2014-07-16T19:16:09

Your output appears to be in octal in the waveform, or base 8 (I'm guessing this is the 'O 000' in the second column).

In this case 'd5 + 'd3 = 'd8 ('o010). So everything seems to be working correctly.

Verilog counter counts wrong

1 Answers