Synthesis Limit..what is this ..?

Question

/*
S0= highway GREEN county RED
S1= Highway YELLOW County RED
S2= highway RED County RED
S3= highway RED County GREEN
s4= Highway RED County YELLOW
*/

/*
X checks the movement on County Road
  =1 means CARS ARE THERE
  =0 means CARS ARE NOT THERE
*/

module sig_ctrl(
  hwy,
  county,
  x,
  clock,
  clear);

  output [1:0] hwy,county;
  reg    [1:0] hwy,county;
  reg    [2:0] pre_state,  next_state;

  reg i = 0;
  input x, clock, clear;

  parameter RED    = 2'b00,
            YELLOW = 2'b01,
            GREEN  = 2'b10;

  parameter s0 = 3'b000,
            s1 = 3'b001,
            s2 = 3'b010,
            s3 = 3'b011,
            s4 = 3'b100,
            s5 = 3'b101;

  always @(posedge clock) begin
    if (clear)
      pre_state <= s0;
    else
      pre_state <= next_state;
  end

  always @(pre_state or x) begin
    case(pre_state)
      s0 : begin
        if (x) 
          next_state = s1;
        else
          next_state = s0;
      end

      s1: @(posedge clock) begin
        begin
          while (i<=3)
            i=i+1;
        end
        begin
          next_state = s2;
        end
      end

      s2: @(posedge clock) begin
        next_state = s3;
      end

      s3: begin
        if(x)
          next_state = s3;
        else
          next_state = s4;
      end
      s4: @(posedge clock) begin
        while (i<=3)
          i=i+1;
        next_state = s0;
      end

      default : next_state = s0;
    endcase
  end

  always @(pre_state) begin
   case(pre_state)
    default :begin hwy = GREEN;county = RED;end
    s0 : ;
    s1 : hwy = YELLOW;
    s2 : hwy = RED;
    s3 : begin
      hwy    = RED;
      county = GREEN;
    end
    s4 : begin
      hwy    = RED;
      county = YELLOW;
    end
  endcase
end
endmodule

This is a verilog code for traffic light simulation.... on compiling this code..I am getting an error at line 45 (where 'always @(pre_state or x)' is written) as synthesis limit. Please help me in removing it.

Thank you

Greg Greg · Accepted Answer · 2014-06-09T16:32:07

Time blocking statements are not allowed in the body of always blocks. The @(posedge clock) in the always @(pre_state or x) is illegal. If you want to wait an additional clock cycle before changing states, then I recommend you add a counter.

while-loops are also not synthesizable. Loops are only synthesizable when the loop count is constant, ex for (i=0;i<3;i=i+1) begin /* nothing that assigns i */ end. Clearly you never simulated your code because i is a single bit will always be less than 3 and is an infinite loop. Even if i had a proper range, it doesn't do anything in the code.

Other issues/recommendations:

hwy and county will synthesize to complex latching logic. Change its always @(pre_state) to always @(posedge clock) and change there assignments from blocking(=) to non-blocking(<=)
change always @(pre_state or x) to always @* or always @(*). Your currently using IEEE1364-1995 syntax. It is legal but there is a risk you will create complex latching logic if don't maintain the sensitivity list. @* and @(*) are synonymous. They were added in in IEEE1364-2001 and are for automatic sensitivity list.
inputs and outputs should be be declared before reg and wire when using the non-ANSI style. I recommend IEEE1364-2001's ANSI style as an alternative. It is less typing, especially when there is a long list of ports:
```
module sig_ctrl(
    output reg [1:0] hwy,county,
    input x,clock,clear ); /* This is IEEE1364-2001's ANSI style */

  reg [2:0]pre_state,next_state;
  integer i = 0;
/...
```

Synthesis Limit..what is this ..?

1 Answers