makefile with variable target

0
votes

I'm attempting to define a Makefile that will take in a filename (eg. foo) as a variable from the command line, and then compile & link using gcc. So if I type make foo it will compile foo.c ,link up foo.o to the required libraries, and clean up the .o file. Here's my code so far, does anyone have any suggestions for where I'm going wrong?

@: [email protected]
        @echo target is $@
        gcc [email protected] -v -lmar -lbar -DDEBUG -o $@
        rm [email protected]

[email protected]: [email protected]
        gcc -c -v [email protected]
1
cmakefile

1 Answers

2
votes

Make already uses the arguments as the target list. And it already has implicit rules that do what you want. You should be able to get away with something like this as your makefile:

LDLIBS=-lmar -lbar
LDFLAGS=-v
CFLAGS=-v