Gate level Verilog syntax

Question

I have the following initiation in gate level Verilog.

bufx2 BH2_BUF (
  .A(\mux_inst/aggr_portd_inst/dskw_inst/ds_mem_slice[4][5] ),
  .Z(\mux_inst/aggr_portd_inst/dskw_inst/ds_mem_slice_4__5_3) 
);

In my poor understanding "Z" pin of buffer is connected to : "\mux_inst/aggr_portd_inst/dskw_inst/ds_mem_slice_4__5_3"

1.But the connection of "A" is not clear.
2.Should be there space between [4] and [5] or not?

Answer 1

Synthesis tools can perform two operations on your design:

• Flattening: They convert your hierarchical design into a single module in which there is no hierarchy. In this case, all signal names in the flatten module corresponding to signals in the non-flatten module mux_inst.aggr_portd_inst.dskw_inst will have the prefix name: \mux_inst/aggr_portd_inst/dskw_inst. The '\' is used to escape '/' character.

• Bit-blasting: Bit-blasting is the term for breaking down a bus/array into its individual members. For example, an array which was originally defined as logic [2:0] array will be broken into:

    logic \array[2] ;
    logic \array[1] ;
    logic \array[0] ;
  

Again, the '\' is used to escape '[' and ']' characters. If they array was two-dimensional, you would have: logic \array[2][0] ;, which acts like a single wire corresponding to member [2][0] of the array.

In your case, it looks like the synthesizer performed both flattening and bit-blasting.

There might be a rare occasion, where the synthesizer performs bit-blasting on only one dimension and keep the other dimension as an array. In that case, \array[2] [0] ; has a different meaning than logic \array[2][0] ;. The former is the member 0 of an array called \array[2], whereas the latter is a single wire which was the result of bit-blasting, corresponding to the index [2][0] of the array before bit-blasting.

Answer 2

With Verilog binary words each bit can be accessed with an array like syntax.

//Create 24 bit word
reg [23:0] a_word;
reg a_bit;

//Access the MSB (bit 23)
initial begin
  a_word    = 24'b0;
  a_bit= a_word[23] ;
end

Extra dimensions can be add, the most basic 2 dimensional array often being called a memory. Here with syntax used previously the first [] access a word, using double [][] we access a single bit.

// Create 24 bit 10 deep memory
reg [23:0] a_memory [0:9];

integer i;
initial begin 
  for (i=0, i<10, i=i+1) begin
    a_memory[i] = 24'b0;
  end

  //Access a word
  a_word = memory[1];

  //Access a bit
  a_word[4] = memory[1][4];
  a_bit     = memory[1][4];
end

Therefore if ds_mem_slice is declared as a memory then \mux_inst/aggr_portd_inst/dskw_inst/ds_mem_slice[4][5] is accessing a single bit of it. Word 4 bit 5.