Signal led cannot be synthesized, bad synchronous description?

Question

I have created a frequency divider, and I want to test it using a FPGA board. To test it I want to make a led flicker with the divided frequency, if a switch is on. The problem is that I do't know how to change the value of the led if clock is not on rising edge.

Here is the exact error I get:

line 51: Signal led cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release. -->

library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity divizor1 is
    Port (clk : in STD_LOGIC;
            --clk_out : out STD_LOGIC;
            btn : in STD_LOGIC;
            led : out STD_LOGIC
            );
end entity divizor1;


architecture divizor_frecv of divizor1 is
    signal cnt : std_logic_vector (24 downto 0);
    signal clock :std_logic;
    signal bec : std_logic;
        begin
            process(clk)
                begin
                    if rising_edge(clk) then
                        cnt<=cnt +1;
                    end if;
                    if (cnt = "1111111111111111111111111") then
                        --clk_out <= '1';
                        clock <= '1';
                    else
                    --  clk_out <= '0';
                        clock <= '0';
                    end if;

            end process;

process (clock, btn)
    begin
        if btn = '1' then
                if clock'event and clock = '1' then
                    led <= '1';
                else
                    led <= '0';
                end if;

        end if;
    end process;



end divizor_frecv;

Answer 1

The error message appears to be complaining that you are using the output of the cnt counter as a clock.

Instead you could use it as a toggle enable and clk as the clock:

--process (clock, btn)
process (clk, btn)
    begin
        -- if btn = '0' then
        if btn = '1' then  -- reset led
            led <= '0';    -- or '1' which ever turns it off
            -- if clock'event and clock = '1' then
        elsif clock = '1' and rising_edge(clk) then -- clock as enable
            -- led <= '1';
            led <= not led;
            -- else
            --     led <= '0';
        end if;

        -- end if;
    end process;

The state of btn made a convenient reset to provide an initial value for led to be able to use not led. This either requires the port signal led be made mode inout or you need a proxy variable or signal which is assigned to led so the not led works (so led can be read). A default value for cnt would also help simulation.

I cheated and made your counter cnt shorter and set the clock to 4 MHz to illustrate:

The simulation was done using ghdl and gtkwave.

Answer 2

process (clock, btn)
begin
    if btn = '1' then
            if clock'event and clock = '1' then
                led <= '1';
            else
                led <= '0';
            end if;

    end if;
end process;

At a first glance, I would have guessed the button was a clock enable here. However, the else part is connected to the clock. So you've asked for led to go high at the rising clock edge and low at all other times; given that the clock edge is an instant, this doesn't make much sense (it would always be low). I expect you want to update led based on some other state on the clock edge, for instance:

process (clock)
begin
    if clock'event and clock = '1' then
        led <= btn;
    end if;
end process;

If all you wanted was for the LED to indicate the clock pulses (which may well be too fast to detect) you could just route clock directly to led. Your divider is already producing very short pulses (usually we aim for 50% duty cycle, this has 0.000003%).