VHDL modify one signal with mutiple clock

Question

I met a problem in using 3 clock in one process if i make a process like this: HC1,HC2 may function at the same time and they are much more slower than H , H is the base clock which works at 16MHZ.

entity fifo is
    Port ( H : in  STD_LOGIC;
           HC1 : in  STD_LOGIC;
           HC2 : in  STD_LOGIC;
           C1data : in  STD_LOGIC_VECTOR (2 downto 0);
           C2data : in  STD_LOGIC_VECTOR (2 downto 0);
           Buffer1 : out  STD_LOGIC_VECTOR (3 downto 0);
           Buffer2 : out  STD_LOGIC_VECTOR (3 downto 0));
end fifo;

architecture Behavioral of fifo is
    signal Full1,Full2 : STD_LOGIC;
begin
process(H,HC1,HC2)
begin
    if(rising_edge(H)) then
        Full1 <= '0';
        Full2 <= '0';
    else
        if(rising_edge(HC1)) then
            Buffer1(3 downto 1) <= C1data;
            Buffer1(0) <= C1data(2) xor C1data(1) xor C1data(0);
            Full1 <= '1';
        end if;

        if(rising_edge(HC2)) then
            Buffer2(3 downto 1) <= C2data;
            Buffer2(0) <= C2data(2) xor C2data(1) xor C2data(0);
            Full2 <= '1';
        end if;
   end if;

end process;

and it says:
ERROR:Xst:827 - "C:/Users/Administrator/Desktop/test/justatest/fifo.vhd" line 45: Signal Buffer1<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

why? Many thanks !

Well, I strongly suggest you to fix your question layout to help us decipher your code first. :D — delirium
What you may need is a single clock and multiple "load" signals or the like. I would also recommend simulating this first to see if it even operates the way you intend, bad synthesis code or not. — fru1tbat
If your were to look in the XST user guide (e.g. UG627 v 14.5) you'd find that an if statement with one clock and and elsif with another isn't a listed as supported under VHDL Sequential Circuits, VHDL Sequential Process With a Sensitivity List. — user1155120
Regarding your error message, I assume the target device is a Xilinx FPGA. But which Xilinx FPGA can support 3 clocks in one hard macro? All internal memory elements are single (FF, SRL, ...) or double clocked (BlockRAM), there are no triple clocked components. Are the signals HC1 and HC2 even real clock signals or more like enable signals. If so, then use a rising edge detection (one FF plus and one AND2B1-gate). Otherwise I would suggest to search for cross clock techniques. — Paebbels

Kevin Thibedeau Kevin Thibedeau · Accepted Answer · 2015-01-27T19:49:19

Not all valid VHDL is synthesizable. What is considered synthesizable varies between tools and the target architecture. The Xilinx hardware architectures have no way to represent the logic described by your code (without resorting to gated clocks). Synthesizers only support a subset of the language and expect hardware primitives to be described using certain "set" templates. Modern tools are more forgiving in what they will accept for a high level description but there is a limit to what they can accomplish.

Digital logic synthesis tools make certain assumptions about the types of circuits they will support. Your circuit description applies the rising_edge() function to three different signals in the same process. Complex clocking arrangements like this are generally not supported. The usual expectation is that a circuit consists of isolated clock domains activated by a single clock edge. They will not automatically create gated clocks to suit atypical code like your example because this introduces potential hazards into the circuit that may not be detected with timing constraints and static timing analysis.

In the case of FPGAs, the clocking architecture is baked in and no amount of fiddling with the input description can change that. Feeding clocks into the logic fabric to be gated upsets the default expectations of the synthesizer and is best avoided if at all possible.

If HC1 and HC2 are actually control signals and not clocks then you shouldn't be using the rising_edge() function to detect changes in their state. Instead you should create delayed versions registered by the common clock H. A change from '0' to '1' is then detected by the expression HC1 = '1' and HC1_prev = '0'.

The else condition to the top level if statement is not supported by XST as it doesn't conform to XSTs expectations for describing synchronous logic. You should instead eliminate the else and move the initialization of Full1 and Full2 to a separate reset/clear section. This can be done synchronously or asynchronously. Refer to the XST synthesis guide for examples on how to accomplish that.

VHDL modify one signal with mutiple clock

1 Answers