Is it syntax correct with gate level Verilog file, where the the sub-modules are defined after the owning module or they should be defined before? Does it matter according to Verilog rules?
Regards,
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3 Answers
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This might be compiler dependent, but if you are using a tool that supports SystemVerilog (which most commercial tools do these days), it should be syntactically correct to define modules in any order, perhaps even in separate files.
See IEEE Std 1800-2012, Section 3.12 for more info.
Notice that after compilation, there is another step which is called elaboration. At that point all the module description should have been compiled correctly. From SystemVerilog LRM:
Compilation is the process of reading in SystemVerilog source code, decrypting encrypted code, and analyzing the source code for syntax and semantic errors. Implementations may execute compilation in one or more passes. Implementations may save compiled results in a proprietary intermediate format, or may pass the compiled results directly to an elaboration phase. Not all syntax and semantics can be checked during the compilation process. Some checking can only be done during or at the completion of elaboration.
SystemVerilog supports both single file and multiple file compilation through the use of compilation units (see 3.12.1).
Elaboration is the process of binding together the components that make up a design. These components can include module instances, program instances, interface instances, checker instances, primitive instances, and the top level of the design hierarchy. Elaboration occurs after parsing the source code and before simulation; and it involves expanding instantiations, computing parameter values, resolving hierarchical names, establishing net connectivity and in general preparing the design for simulation.
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The short answer is that you can forward-reference modules in Verilog; this has always been the case, and is not tool-dependent (in other words, you can do it in either order). There may be complications if you use libraries and configurations but, in general, you can assume that you can instantiate a module before it is defined.
In most of Verilog, you have to declare something before you reference it. There are some exceptions, including task and function calls, implicit wires, cross-module/hierarchical references, and module names. In these cases, the tool waits until elaboration to find the referenced object. There is no clear explanantion of much of this in the LRM, unfortunately. This is how Verilog-XL did it, and everyone else has done it ever since.
Note that this isn't related to 'gate-level' files.
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According to the rules defined in the Verilog LRM, modules, functions and tasks are the only things that may be referenced before being declared. SystemVerilog adds interfaces and programs to that list. Verilog also has implicitly declared nets that makes it seem that you are referencing a net before it being declared, but I strongly suggest not using that feature by using the compile directive ``default_nettype none.
