system verilog interface for multiple clocks

Question

My DUT is a memory controller. I have to write a system verilog interface for the DUT. Memory Controller DUT supports 32 AXI Masters. When I am writing an AXI interface, it will consist of ACLK which is generated and passed on through the top(verification). When I am connecting this interface to the DUT, will there be 32(AXI ACLK) + 1(clk on which DUT is working) , inall 33 clks to the DUT.. I am quite confused in these. logically there should be only one clk in the DUT..

Thanks in advance for the answers

dave_59 dave_59 · Accepted Answer · 2014-04-21T14:47:32

Shared interface signals should be declared as input ports to your interface. That way you can tie them all together to make one logical signal.

interface myintf(input wire sig_shared);

  wire sig_internal;

endinterface

module top;

  wire s1,s2;

  myintf i1(s1);
  myintf i2(s1);

  myintf i[31:0](s2);

endmodule

Now signals i1.sig_internal and i2.sig_internal will be independent, but i1.sig_shared and i2.sig_shared are logically equivalent. Same thing for i[0].sig_shared thru i[31].sig_shared.

system verilog interface for multiple clocks

1 Answers