Finite State Machine Verilog 4 num sequence

Question

Ok so I know my code works for a 3 number sequence but for with the finite state machine model I drew out this should be correct but it doesn't work for a 4 number sequence. It only detects the first 3. I need to detect with an overlap "0110" from the sequence 01100110110111. It should have 3 "0110" sequences and 2 overlapping but when I run my Verilog it detects 4 "0110" sequences which tells me it's only grabbing "011" Can someone look at my code and see what I'm doing wrong? I could simply add another state but I wouldn't think that's the correct way since I don't have another state in my diagram.

module moore_seq
(
        input clock, reset, x,
        output reg z
);

//assign binary encoded codes to the states A through D
parameter       A = 2'b00,
                B = 2'b01,
                C = 2'b10,
                D = 2'b11;

reg [1:0] current_state, next_state;

//Section 1: Next state generator (NSG)
always@(*)
begin
        casex(current_state) //ignore unknown and Hi-Z inputs
        A:      if (x == 1)
                        next_state = A;
                else
                        next_state = B;
        B:      if (x == 1)
                        next_state = C;
                else
                        next_state = B;
        C:      if (x == 1)
                        next_state = D;
                else
                        next_state = B;
        D:      if (x == 1)
                        next_state = A;
                else
                        next_state = B;
        endcase
end
//Section 2: Output Generator (OG)
always@(*)
begin
        if(current_state == D)
                z = 1;
        else
                z = 0;
end

//Section 3: The Flip Flops
always@(posedge clock, posedge reset)
begin
        if(reset == 1)
                current_state <= A;
        else
                current_state <= next_state;
end
endmodule

UPDATED:

parameter       A = 3'b000,
                B = 3'b001,
                C = 3'b010,
                D = 3'b011,
                E = 3'b100;

reg [1:0] current_state, next_state;

//Section 1: Next state generator (NSG)
always@(*)
begin
        casex(current_state) //ignore unknown and Hi-Z inputs
        A:      if (x == 1)
                        next_state = A;
                else
                        next_state = B;
        B:      if (x == 1)
                        next_state = C;
                else
                        next_state = B;
        C:      if (x == 1)
                        next_state = D;
                else   
                        next_state = B;
        D:      if (x == 1)
                        next_state = A;
                else
                        next_state = E;
        E:      if (x == 1)
                        next_state = C;
                else
                        next_state = B;
        endcase
end

//Section 2: Output Generator (OG)
always@(*)
begin
        if(current_state == E)
                z = 1;
        else
                z = 0;
end

You must need more states because you reach D after 3 inputs (causing A->B, B->C, and C->D). — Ben Jackson
Thought so, my diagram didn't have another state so that's why I didn't put it in. I'm not sure I know how to add another state under the parameters. Would it be something like E = 2'b111; ? — user2318083
You need more bits in your state variables (declarations not shown in your code) and your state constants would have to be 3 bits wide (i.e. 3'b...) as well. — Ben Jackson
Updated my code but now it won't detect any "0110" which is z = 1 correctly. — user2318083
You need more bits in your state variables: 3 bits does not fit in a reg [1:0] — Ben Jackson

Alexey Birukov Alexey Birukov · Accepted Answer · 2015-01-30T11:43:12

I suppose, four states is enough. Just change

//Section 2: Output Generator (OG)
always@(*)
begin
    if(current_state == D)

to

//Section 2: Output Generator (OG)
always@(*)
begin
    if(current_state == D && x == 0 )

Finite State Machine Verilog 4 num sequence

1 Answers