led pattern finite state machine verilog

Question

I was wondering if someone could shed some light on how to go about coding a led pattern fsm in verilog that produces the 4 different patterns on 8 LEDs and the LEDs change every tick pulse, there are 4 buttons to trigger 4 different modes, each mode will trigger 8 LEDs to move in a pattern, i.e. left to right, right to left.

I've written a sequential logic but I don't know how to go about inserting the patterns for the LEDs into each state. Heres my code:

`timescale 1ns / 1ps
module pattern_fsm(
input [3:0] mode,
input tick,
input clk,
input reset,
output reg [7:0] Led
);

 reg [3:0] state, nextstate;

 parameter s0 = 4'b0001;
 parameter s1 = 4'b0010;
 parameter s2 = 4'b0100;
 parameter s3 = 4'b1000;

 always @(posedge clk, posedge reset)
    if(reset) 
        state <= s0;
    else
        state <= nextstate;

always @(*)
    begin
        case(state)
            s0: if(mode == 4'b0001) nextstate = s0;
                    else nextstate = s3;
            s1: if(mode == 4'b0010) nextstate = s1;
                    else nextstate = s0;
            s2: if(mode == 4'b0100) nextstate = s2;
                    else nextstate = s1;
            s3: if(mode == 4'b1000) nextstate = s3;
                    else nextstate = s2;
            default: nextstate = s0;
        endcase
    end

always @(state)
    begin
        case(state)
            s0: Led = 8'b00000001;
            s1: Led = 8'b00000010;
            s2: Led = 8'b00000011;
            s3: Led = 8'b00000100;
        endcase
    end

endmodule

Marty Marty · Accepted Answer · 2012-10-12T16:34:57

Maybe you could use shift operations?

always @(posedge clk or posedge reset )
    if(reset) begin
        Led <= 8'h00;
    end
    else begin
        case(state)
            s0: Led <= 8'h01;              // a single Led lit 
            s1: Led <= {Led[0], Led[7:1]}; // rotate right
            s2: Led <= {Led[6:0], Led[7]}; // rotate left
            s3: Led <= ~Led;               // flip?
            default: Led <= Led;           // do nothing
        endcase
    end

I hope you found this illuminating. I haven't tested this code, so beware...

led pattern finite state machine verilog

1 Answers