I am trying to implement 32x32 Register File in VHDL. I have been struggling with this issue for a while... More specifically, I get the following error when I try to compile the code:
HDLParsers:164 - "//vmware-host/shared folders/Shared from MAIN/decoder.vhd" Line 26. parse error, unexpected STRING_LITERAL, expecting PIPE or ROW
I have tried variety of different solutions and none of them worked. I am placing all the entities as they appear in the top level system. The top level system:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.array_pkg.all;
entity GenRegisters is
port( Rd_Data : in std_logic_vector(31 downto 0);
Rs, Rt, Rd : in std_logic_vector(4 downto 0);
Reg_Write : in std_logic; -- enable
Rs_Output: out std_logic_vector(31 downto 0);
Rt_Output: out std_logic_vector(31 downto 0);
CLK, RESET : in std_logic -- clock and reset
);
end GenRegisters;
architecture Behavioural of GenRegisters is
signal decoder_out : std_logic_vector(31 downto 0);
signal DOUT: std_logic_vector(31 downto 0);
-- component declaration
component Register32
port (
DIN : in std_logic_vector(31 downto 0); -- system inputs
DOUT : out std_logic_vector(31 downto 0); -- system outputs
ENABLE : in std_logic_vector (0 downto 0); -- enable
CLK, RESET : in std_logic -- clock and reset
);
end component; -- end component;
-- component declaration
component Mux32t5
port (
Registers : in array2d; -- system inputs
Rselect : in std_logic_vector(4 downto 0);
Rout : out std_logic_vector(31 downto 0) -- system outputs
);
end component; -- end component;
-- component declaration
component decoder
port (
enable : in std_logic; -- enable
binary_in: in std_logic_vector(4 downto 0); -- system inputs
decoder_out: out std_logic_vector(31 downto 0) -- system outputs
);
end component; -- end component;
begin
-- VHDL Generalte allows you to replicate components, see hep
Decoder_1: decoder
port map(Reg_write, Rd, decoder_out);
GEN_ADD: for I in 0 to 31 generate
Register32D:Register32 port map
(Rd_Data, DOUT, decoder_out(I), CLK, RESET); -- :)
end generate GEN_ADD;
Mux_Rt: Mux32t5
port map(Register32D, Rt, Rt_Output);
Mux_Rs: Mux32t5
port map(Register32D, Rs, Rs_Output);
end Behavioural;
Decoder entity:
-------------------------------------------------------
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(
enable :in std_logic; -- Enable for the decoder
binary_in :in std_logic_vector (4 downto 0); -- 5-bit Input
decoder_out :out std_logic_vector (31 downto 0) -- 32-bit Output
);
end decoder;
architecture Behavioural of decoder is
begin
process (enable, binary_in)
begin
decoder_out <= X"00000000";
if (enable = '1') then
case (binary_in) is
when 5x"00" => decoder_out <= X"00000001";
when 5x"01" => decoder_out <= X"00000002";
when 5x"02" => decoder_out <= X"00000004";
when 5x"03" => decoder_out <= X"00000008";
when 5x"04" => decoder_out <= X"00000010";
when 5x"05" => decoder_out <= X"00000020";
when 5x"06" => decoder_out <= X"00000040";
when 5x"07" => decoder_out <= X"00000080";
when 5x"08" => decoder_out <= X"00000100";
when 5x"09" => decoder_out <= X"00000200";
when 5x"0A" => decoder_out <= X"00000400";
when 5x"0B" => decoder_out <= X"00000800";
when 5x"0C" => decoder_out <= X"00001000";
when 5x"0D" => decoder_out <= X"00002000";
when 5x"0E" => decoder_out <= X"00004000";
when 5x"0F" => decoder_out <= X"00008000";
when 5x"10" => decoder_out <= X"00010000";
when 5x"11" => decoder_out <= X"00020000";
when 5x"12" => decoder_out <= X"00040000";
when 5x"13" => decoder_out <= X"00080000";
when 5x"14" => decoder_out <= X"00100000";
when 5x"15" => decoder_out <= X"00200000";
when 5x"16" => decoder_out <= X"00400000";
when 5x"17" => decoder_out <= X"00800000";
when 5x"18" => decoder_out <= X"01000000";
when 5x"19" => decoder_out <= X"02000000";
when 5x"1A" => decoder_out <= X"04000000";
when 5x"1B" => decoder_out <= X"08000000";
when 5x"1C" => decoder_out <= X"10000000";
when 5x"1D" => decoder_out <= X"20000000";
when 5x"1E" => decoder_out <= X"40000000";
when 5x"1F" => decoder_out <= X"80000000";
when others => decoder_out <= X"00000000";
end case;
end if;
end process;
end Behavioural;
Register32:
-------------------------------------------------------
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Register32 is
port (
DIN : in std_logic_vector(31 downto 0); -- system inputs
DOUT : out std_logic_vector(31 downto 0); -- system outputs
ENABLE : in std_logic_vector(0 downto 0);
CLK, RESET : in std_logic -- clock and reset
);
end Register32;
architecture Behavioural of Register32 is
begin
process(CLK,RESET)
begin -- process
-- activities triggered by asynchronous reset (active high)
if RESET = '1' then DOUT <= "00000000000000000000000000000000";
-- activities triggered by rising edge of clock
elsif CLK'event and CLK = '1' then
if ENABLE='1' then DOUT <= DIN;
else null;
end if;
end if;
end process;
end Behavioural;
MUX_Rt:
-------------------------------------------------------
-------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.array_pkg.all;
-- define inputs and outputs
entity Mux32t5 is
port(
Registers : in array2d;
RSelect : in std_logic_vector(4 downto 0);
Rout : out std_logic_vector(31 downto 0) );
end Mux32t5;
architecture Behavioural of Mux32t5 is
begin
with Rselect select
Rout <= Registers(0) when 5X"00",
Registers(1) when 5X"01",
Registers(2) when 5X"02",
Registers(3) when 5X"03",
Registers(4) when 5X"04",
Registers(5) when 5X"05",
Registers(6) when 5X"06",
Registers(7) when 5X"07",
Registers(8) when 5X"08",
Registers(9) when 5X"09",
Registers(10) when 5X"0A",
Registers(11) when 5X"0B",
Registers(12) when 5X"0C",
Registers(13) when 5X"0D",
Registers(14) when 5X"0E",
Registers(15) when 5X"0F",
Registers(16) when 5X"10",
Registers(17) when 5X"11",
Registers(18) when 5X"12",
Registers(19) when 5X"13",
Registers(20) when 5X"14",
Registers(21) when 5X"15",
Registers(22) when 5X"16",
Registers(23) when 5X"17",
Registers(24) when 5X"18",
Registers(25) when 5X"19",
Registers(26) when 5X"1A",
Registers(27) when 5X"1B",
Registers(28) when 5X"1C",
Registers(29) when 5X"1D",
Registers(30) when 5X"1E",
Registers(31) when 5X"1F",
X"0000" when others;
end Behavioural;
MUX_Rs:
-------------------------------------------------------
-------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.array_pkg.all;
-- define inputs and outputs
entity Mux32t5 is
port(
Registers : in array2d;
RSelect : in std_logic_vector(4 downto 0);
Rout : out std_logic_vector(31 downto 0) );
end Mux32t5;
architecture Behavioural of Mux32t5 is
begin
with Rselect select
Rout <= Registers(0) when 5X"00",
Registers(1) when 5X"01",
Registers(2) when 5X"02",
Registers(3) when 5X"03",
Registers(4) when 5X"04",
Registers(5) when 5X"05",
Registers(6) when 5X"06",
Registers(7) when 5X"07",
Registers(8) when 5X"08",
Registers(9) when 5X"09",
Registers(10) when 5X"0A",
Registers(11) when 5X"0B",
Registers(12) when 5X"0C",
Registers(13) when 5X"0D",
Registers(14) when 5X"0E",
Registers(15) when 5X"0F",
Registers(16) when 5X"10",
Registers(17) when 5X"11",
Registers(18) when 5X"12",
Registers(19) when 5X"13",
Registers(20) when 5X"14",
Registers(21) when 5X"15",
Registers(22) when 5X"16",
Registers(23) when 5X"17",
Registers(24) when 5X"18",
Registers(25) when 5X"19",
Registers(26) when 5X"1A",
Registers(27) when 5X"1B",
Registers(28) when 5X"1C",
Registers(29) when 5X"1D",
Registers(30) when 5X"1E",
Registers(31) when 5X"1F",
X"0000" when others;
end Behavioural;
array_pkg: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
package array_pkg is
TYPE array2d IS ARRAY(31 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
END array_pkg;
Can anyone provide some clues or solution for the problem please?
