0
votes

I'm somewhat stumped on this problem:

"Write a verilog module for full addition of n-bit integers. Let the parameter, the number of bits, equal 3. Call this module from a test bench, and in the test bench specify the numbers to be added in the arrays. Assign octal values to the X and Y arrays. The carryin is 0."

And yes, this is homework.

I was able to write the module for the n-bit adder:

module addern(carryin, X, Y, S, carryout, overflow);
  parameter n = 3;
  input carryin;
  input [n-1:0] X, Y;
  output reg [n-1:0] S;
  output reg carryout, overflow;

  always @(X,Y, carryin)
    begin 
      {carryout, S} = X + Y + carryin;
      overflow = (X[n-1] & Y[n-1] & ~S[n-1]) | (~X[n-1] & ~Y[n-1] & S[n-1]);
    end

endmodule   

I understand this component of the problem. However, I'm not sure how to implement the octal number addition. Is there a way in verilog to indicate that the arrays are holding octal values, rather than binary?

Is there anything like a typecast in verilog? For instance, input (octal) [n-1:0] X, Y, and do something likewise in the test bench.

Any constructive input is appreciated.

2
You don't need to; just take the bits of your overall number in groups of three.Oliver Charlesworth
Good point. So would I simply change by parameter n to 9? My only concern is how the problem is worded. For instance, farther down the page it says to explicitly set X to [0,1,3].Mlagma
All they're asking you to do is assign an octal literal to X - x = 9'o013Eric
That makes sense. If I do that, is verilog intelligent enough to add the numbers in octal, being that parameter n = 3;?Mlagma
Octal, hex and decimal are just ways of visualising numbers at the end of the day they are binary when stored digitally.Morgan

2 Answers

0
votes

I'm pretty sure I'm in the same class as you. I think what you need to do is create a hierarchical Verilog module and then assign your values there. That would be your testbench. for example if you want to make X you write input [n-1:0] X = 3'o013, or maybe it's X = 9'o013 if Oli is correct. you don't change n, but it's kind of like BCD where they are in groups and you have a certain amount of bits you can represent before it overflows.

0
votes

To help solve the problem thik about the question:
Q) How are numbers stored in digital hardware?
A) Binary, in digital logic we can only represent 2 values 1 and 0, but with this we can represent Integer, fixed point or floating point numbers.

Therefore digital numbers are base 2 (two possible values), while being able to represent any number. Other bases such as Octal (base 8) hex (base 16) and decimal (base 10) exist but these are just way of representing numbers, similar to the way binary just represents a number.

A decimal 1, is represented by 1 n all the bases, and when stored as binary they are all the same. An example of some values in verilog and there binary equivalents.

Octal    Decimal   Hex     Binary
3'O7  => 3'd7   => 3'h7 =>    3'b111
6'O10 => 6'd8   => 6'h8 => 6'b001000

Octal, Decimal and Hex in verilog are just representations of a binary format, a way of viewing the data. Since the low level electronics has no way of representing any thing other than 0 and 1.

The interesting thing about Octal and Hex is that they have a power of 2 values so they use an exact number of bits so an 9'O123 is the same as treating each Octal place separately and concatenating them together, 9'O123 == {3'O1, 3'O2, 3'O3}. This is also true for hexadecimal values but not decimal (base 10) values, as 10 is not a power of 2 and does not fully occupy the number space.

This does allow 'Octal' ports to be created, which are just 3 bit binary ports:

module octal_concat (
  input  [2:0] octal_2,
  input  [2:0] octal_1,
  input  [2:0] octal_0,
  output [8:0] concat
);
  assign concat = {octal_2, octal_1, octal_0};
endmodule

octal_concat octal_concat_0 (
  .octal_2(3'O1), 
  .octal_1(3'O2), 
  .octal_0(3'O3),  
  .concat() //Drives 9'O123 which is also 9'b001_010_011
);