I have a codebase that runs fine on the M3 architecture and am porting some code to the M0+. I am getting faults and I cannot figure out why. The exact micro I am on is the KL36Z128 (Freescale). I am using ARM-GCC-2013-Q3 release for my toolchain.
So here is the C code (it's for parsing packets as they come in so once I get enough data I just start picking out what I need to fill out the command structures):
state->cmd = *((U16*)&din[15]); // the codebase has 'legacy' type definitions
The assembly generated is:
0x4250 <+0x0014> adds r1, #15
0x4252 <+0x0016> ldrh r1, [r1, #0] <--- Faulting instruction!
0x4254 <+0x0018> strh r1, [r0, #2]
And the register values are at the time of the fault are:
r0 = 0x1ffff2cc r1 = 0x1ffffad8
I have no idea what is happening here - this seems pretty straightforward assembly. And the addressing seems OK. The Freescale datasheet says that RAM is banked with 2 sections:
SRAM_L: (0x20000000-1KB) to 0x20000000 (so it's lower section is 1/4 of the total SRAM)
SRAM_H: 0x20000000 to (0x20000000+3KB)
I originally thought that maybe something was amiss with the code being generated and what instructions can be used to access memory in the different banks - but I came up empty.
Also, the 'din' value is defined in the functions parameter list as: const U8 *din
Any thoughts?
din
of type array ofuint8_t
? In that case you are violating alignment rules! – ouahuint8t_t
object as anuint16_t
object. Cortex-M0+ does not support unaligned access and an attempt to perform an unaligned access raises an HardFault. – ouah