UNALIGNED Usage Fault on LDR instruction-CortexM7

Question

I am debugging an assembly code written for a CortexM7 target. Inside the busFault handler there is a LDR instruction which when executed causes a UNALIGNED Usage Fault and as a result a forced Hard Fault occurs. What I know is that by default there is no address alignment requirement for ldr instruction. I have also checked the the bit in CCR register which can enforce the requirement but it is disabled. Following is my code:

global          c_AbcFunction

c_Abc        .long c_AbcFunction    

BusFaultHandler:
LDR R1, c_Abc

Compiler: ARM-GHS 2017 Debugger: Lauterbach

Value of CCR:

 CCR  00040200  BP           Enabled            IC            Disabled   DC             Disabled
                STKALIGN     8-byte/adjustment  BFHFNMIGN     Lockup     DIV_0_TRP      Disabled
                UNALIGN_TRP  Disabled           USERSETMPEND  Disabled   NONBASETHRDENA Disabled

Disassembly of above code:

0128      c_Abc:        align   0x128
2802                                       ////////                 ; instruction would span across HLL line symbol

BusFaultHandler:
    LDR R1, c_Abc
F85F102E   ldr     r1,0x10013318

The change I made in for strict Alignment:

c_Abc  .long   c_AbcFunction
.align    4

Disassembly after adding ".align 4":

28020128  c_Abc:        stmdacs r2,{r3,r5,r8}

BusFaultHandler:
    LDR R1, c_Abc
F85F1030                                   ldr     r1,0x10013318    ; r1,c_Abc

The underlying issue is somehow fixed by adding .align 4. But I cannot understand the reason as LDR should not have any alignment requirement in the current scenario.

Is your c_Abc actually aligned? Use .p2align 2 before it to insert padding to reach a 2^2 = 4 boundary, or whatever other directive your assembler uses. — Peter Cordes
@old_timer Value of CCR is 00040200 and the UNALIGN_TRP flag is disabled. — SS01

D Krueger D Krueger · Accepted Answer · 2019-06-20T23:50:52

The alignment fault may have nothing to do with the LDR instruction. A misaligned Vector Table seems a more likely culprit. Check to see if the table is on at least a 128 byte boundary. If not, the vector fetch may be the actual source of the fault.

Also, your listing shows align 0x128, but that directive typically requires a power-of-two. Should it be align 128 instead?

UNALIGNED Usage Fault on LDR instruction-CortexM7

1 Answers