Digital frequency doubler with a dual edge triggered flip flop in VHDL

Question

I am trying to implement a digital input frequency doubler. The circuit consists of an XOR2 gate, dual edge triggered flip flop and a couple of buffers.

The frequency-in goes to one of the Xor inputs. The output of the Xor gate goes through a buffer and into the clock signal of the DFF. The output(ussually Q) used in parallel to feed the remaining Xor input and to feedback to the D input of the flip flop through a buffer. finally the output of the doubler is taken from the Xor gate.

I have tested the circuit and it works.I am a novice in VHDL and have very basic knowledge in verilog. I figured i'd analyse it for practice so that i get a feel of VHDL before third year.

Regards Stranger

Sounds interesting. Did you have a question? You might also want to look at SO's EE site, where things like VHDL and Verilog get discussed more often. — Jerry Coffin
If FPGA is target, then consider using a PLL or DCM; maybe this question with answers can help you. — Morten Zilmer

user3250886 user3250886 · Accepted Answer · 2014-02-16T23:21:53

if anyone in the future is suffering the same fate I am here is the ALMOST FINISHED. all you gotta do is find a way of using clk'event in place of if (clk ='1' and clk'EVENT). Schematic is here

    entity freq_doubler is 
PORT (
        vin : in BIT ;
        vout : out BIT );
 end entity freq_doubler;

 architecture rtl of freq_doubler is 
 signal q : bit;
 signal d,clk,buff : bit ;


 begin 
  buff <= (vin XOR q);
  clk <= buff;
  vout <=buff;
p0: process (d,clk) is
    begin
    if (clk ='1' and clk'EVENT)  then
        q <=d;
    end if;
    end process p0;
end architecture rtl;


 configuration freq_doubler_conf of freq_doubler is 
for rtl
end for;
end configuration freq_doubler_conf;

Digital frequency doubler with a dual edge triggered flip flop in VHDL

1 Answers