I'm new to vhdl, and I have simple code to simulate the slt operation; however, I am getting the following error: Error (10500): VHDL syntax error at SetLessThan.vhd(14) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Can anyone help? (Code pasted below) I tried placing ()'s around a < b but that gave me 2 additional errors.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SetLessThan is
port(
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
cout : out std_logic_vector(7 downto 0)
);
end SetLessThan;
architecture dataflow of SetLessThan is
begin
if a < b then
cout <= '00000001';
else
cout <= '00000000';
end if;
end dataflow;