Getting syntax errors

Question

I keep getting errors. They are stated as syntax errors but I believe there are further issues.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity bottlefill is
port (  clk, reset: IN STD_LOGIC;
        b, p: in std_logic;
        m, v: out std_logic;
);

end bottlefill;

ARCHITECTURE a of bottlefill is
type state is (stopped, posi, fill);
signal current1, next1: state;
signal c: integer range 0 to 15;
signal full: std_logic; 

begin
process(clk, reset)
begin
    if reset = '1' then
        current1 <= stopped;
        elsif clk'event and clk = 1
                then current1 <= next1;
        end if;
end process;

process(current1, b, p, stop)
begin
    next1 <= current1;
    case current1 is
    when stopped =>
        if b = '1' then
                next1 <= posi;
                end if;
                m = '1';
                v = '0';
    when posi =>
        if p = '1' then 
                next1 <= fill;
                end if;
                m = '0';
                v = '1';
    when fill  =>
        if full = '1' then
                next1 <= stopped;
                end if;
                m = '0';
                v = '0';
    end case;
end process;


process(clk reset)
begin
    if reset = '1'
        then c <= 0;
    elsif clk'event and clk = '1' 
        then if current1 = fill
            then c <= c + 1;
        else
            c <= 0;
        end if
    end process;

    full <= '1' when c >= 5
        else '0';

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bottlefill -c bottlefill
Error (10500): VHDL syntax error at bottlefill.vhd(9) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at bottlefill.vhd(14) near text ")"; expecting ":", or ","
Error (10500): VHDL syntax error at bottlefill.vhd(19) near text "begin"; expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at bottlefill.vhd(29) near text ")"; expecting ":", or ","
Info: Found 0 design units, including 0 entities, in source file bottlefill.vhd

"but I believe there are further issues." Nope: you have a syntax error and exactly where the compiler says it. In a port definition there is no closing semicolon. m, v: out std_logic ); I have not checked the rest but I strongly suggest that if a compiler says you have a syntax error that you believe it. — Oldfart

Jens Vanhulst Jens Vanhulst · Accepted Answer · 2019-06-15T09:35:05

I have corrected you code so that it has no syntax errors anymore. The only thing that you have to check is te code on line 68. I didn't understand what you wanted to do there.

I commented your syntax mistakes so you could see what was causing the errors.

I hope this helped you a bit.

   LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.numeric_std.all;

    entity bottlefill is
    port (  clk, reset: IN STD_LOGIC;
            b, p: in std_logic;
            m, v: out std_logic -- First mistake here
    );

    end bottlefill;

    ARCHITECTURE behavioral of bottlefill is
        type state is (stopped, posi, fill);
        signal current1, next1: state;
        signal c: integer range 0 to 15;
        signal full: std_logic; 
    begin

    process(clk, reset)
    begin
       if reset = '1' then
           current1 <= stopped;
       elsif clk'event and clk = '1' then -- Mistake with clk = 1 => clk = '1'
           current1 <= next1;
       end if;
    end process;

    process(current1, b, p) -- Stop is not declared here
    begin
       next1 <= current1;
     case current1 is
       when stopped =>
        if b = '1' then
                next1 <= posi;
                end if;
                m <= '1'; -- = is not <= signal assignment !!
                v <= '0'; -- = is not <= signal assignment !!
       when posi =>
        if p = '1' then 
                next1 <= fill;
                end if;
                m <= '0'; -- = is not <= signal assignment !!
                v <= '1'; -- = is not <= signal assignment !!
       when fill  =>
        if full = '1' then
                next1 <= stopped;
                end if;
                m <= '0'; -- = is not <= signal assignment !!
                v <= '0'; -- = is not <= signal assignment !!
        end case;
      end process;


     process(clk, reset) -- komma here
     begin
      if reset = '1' then 
        c <= 0;
        elsif clk'event and clk = '1' then 
            if current1 = fill then 
                c <= c + 1;
            else
                c <= 0;
            end if; -- forgot ;
        end if; -- forgot to close the upper is statement
      end process;

    -- i dont get what u want to do here. Take a look at " Select signal assigment" on  google
    -- I think you want to do that.
    --full <= '1' when c >= 5
                --else '0';

      end behavioral; -- forgot to end your architecture

Getting syntax errors

1 Answers