Flip flop with load/set, reset, clk, and input

Question

I'm not looking for a hardware language description of the flip flop, but the logic gate level to implement.

In verilog, the equivalent I'm looking for is:

always@(posedge clk or negedge reset) begin
  if(~reset)
    Q <= 1'b0;
  else if(~load)
    Q <= D;
end

I've looked at: http://reviseomatic.org/help/e-flip-flop/4013%20D-Type%20Flip%20Flop.php and http://www.csee.umbc.edu/~squire/images/dff.jpg

the problem with the above implementation is that after I set a value to Q (D=0,Q=0,load=0) with load(set in picture) = 0, then when i set load high load = 1 on the next clk cycle, i get (D=x,Q=1,load=1). In order words, changing load from true to false will change the value of Q, but I want Q to hold it's previous value.

What is a flip flop that would hold it's value on Q after it has been set and enable is set high?

Answer 1

You should try looking up a mux flop.

It has a mux in front of the standard d-type and connects it input to output when load is not selected.

Answer 2

Your problem is that 'synchronous load enable' is not the same as 'asynchronous set'. Your Verilog code shows a F/F with an async reset, and a synchronous load enable. Your first (reviseomatic) reference is just nonsense - ignore it. It attempts (wrongly) to describe a 4013, which doesn't have a load enable. I haven't looked at the second reference in detail, but it looks like a conventional latch-based implementation of a F/F with async active-low set and reset.

You can implement flops in several ways:

1. For a CMOS transmission-gate flop implementation, see the NXP datasheet for a 4013
2. For latch-based TTL, see the datasheet for a 7474
3. The old TI databooks used to show flop implementations using async feedback circuits.

For the synchronous load control part, look at Morgan's mux link.