i'm trying to connect 2 modules differently depending on bit_proc_rw signal value.
Can't post pictures yet, so:
if bit_proc_rw dataflow: bit_in --> SCR --> CRC --> bit_out
if not, it's a reciever: bit_in --> CRC --> SCR --> bit_out
So I did this in a top module(all wire-type):
assign SCR_input = (bit_proc_rw) ? bit_proc_in : CRC_output;
assign SCR_input_dav = (bit_proc_rw) ? bit_proc_in_dav : CRC_output_dav;
assign SCR_output = (bit_proc_rw) ? CRC_input : bit_proc_out;
assign SCR_output_dav = (bit_proc_rw) ? CRC_input_dav : bit_proc_out_dav;
assign CRC_input = (bit_proc_rw) ? SCR_output : bit_proc_in;
assign CRC_input_dav = (bit_proc_rw) ? SCR_output_dav : bit_proc_in_dav;
assign CRC_output = (bit_proc_rw) ? bit_proc_out : SCR_input;
assign CRC_output_dav = (bit_proc_rw) ? bit_proc_out_dav : SCR_input_dav;
crc_gen crc_gen_u (
.clk (clk),
.crc_in (CRC_input),
.crc_in_dav (CRC_input_dav),
.crc_out (CRC_output),
.crc_out_dav (CRC_output_dav),
.bit_proc_rw (bit_proc_rw),
);
scr scr_u (
.clk (clk),
.scr_in (SCR_input),
.scr_in_dav (SCR_input_dav),
.scr_out (SCR_output),
.scr_out_dav (SCR_output_dav),
.bit_proc_rw (bit_proc_rw)
);
Testbench shows that only inputs are being driven(ex. rw=0 CRC input works but rest are of unknown value). Is it because i'm assigning both input to output and output to input at the same time? Or is this correct and i should look for bugs in my code? If not, how to do this using only 1 instance of each module?
Hope I made everything clear and thanks for your time!