Comparison Not Functioning Like It Should

0
votes

I am trying to build a module that accepts two 16 bit inputs and depending a compare signal, evaluates a certain expression and sends a true (1) value to choice the output if the expression is evaluated as true.

This is my source code:

    module comparator(input [15:0] r15_register, sourceone_register , input [1:0] comp_signal, output reg choice);
    always @(*)begin
        if (comp_signal == 2'b00) begin
            //Check if soureceone is greater than r15.
            choice = (sourceone_register > r15_register)? 1:0;          
            end
        else if (comp_signal == 2'b01) begin
            //Check is sourceone is less than r15.
            choice = (sourceone_register <r15_register)? 1:0;
            end
        else if (comp_signal == 2'b10) begin
            //Check if sourceone is equal to r15.  
            choice = (sourceone_register == r15_register)? 1:0;
            end
        else
            choice <= 0;
    end 
endmodule

This is my testbench code:

module comparator_fixture();
reg [15:0] r15_register, sourceone_register;
reg [1:0] comp_signal;
wire choice;

comparator utt(.r15_register(r15_register), .sourceone_register(soureone_register), .comp_signal(comp_signal), .choice(choice));

initial begin
    #20;
    comp_signal = 2'b00;
    //Sourceone is greater than r15.
    r15_register = 4;
    sourceone_register = 6;
    //Sourceone is less than r15.
    #10;
    comp_signal = 2'b01;
    r15_register = 6;
    sourceone_register = 4;
    //Sourceone is equal to r15.
    #10;
    comp_signal = 2'b10;
    r15_register =7;
    sourceone_register =7;
    #30;
    $stop;
end

endmodule

When a comp_signal is given, it drives the output choice to X (an unknown state), and I haven't been able to figure out why. Can someone please offer some advice?

Here is the waveform.

2
verilog
It drives output to 'x' when? all the 60s which you simulated? what does it mean "when a com_signal is given"? - Serge
When I say "when a comp_signal is given" I mean that the signal can either be 2'b00, 2'b01, or 2'b10 and depending on what that input is, it is suppose to compare if the sourceone contents are greater than, less than or equal to r15's contents. - user12459099
I uploaded a waveform to show when it goes to X. Thank you for any help. - user12459099

2 Answers

0
votes

I put your code into Vivado and get errors:

  • undeclared symbol soureone_register, assumed default net type wire ...
  • unexpected EOF

I found your waveform already 'weird' as choice was zero while nothing else had been given a value yet. So whatever you used to produce that waveform, it can't be the code you showed.

After I fixed the errors choice is no longer X.

0
votes

Found my error, in my fixture there was an error in how I spelled "source" during the instantiation. I have included a waveform of the run after I fixed my spelling error.

Here is the waveform with the correct output of "choice".