convert a std_logic_vector INPUT to IEEE Float type

0
votes

How convert a std_logic_vector INPUT of the my entity in a IEEE Float type, to do some operations in my process? My entity need receive a IEEE Float of A/D converter.

2
vhdlxilinxhdlintel-fpga
What exactly do you need to do? Convert integer data that comes from the ADC into floating-point? – geschema
Not integer. Float value from ADC in IEEE form to BCD form – Antônio Vieira
What ADC produces floating point outputs? – Martin Thompson
the question don't is this – Antônio Vieira

2 Answers

1
votes

VHDL doesn't have a float type by default - it has real which is not synthesisable.

However, the IEEE-standardised VHDL floating-point types are perfectly synthesisable.

You'll have to cast your std_logic_vector as an unsigned or signed vector first and then convert to a suitable floating-point type, which need not be an IEEE-754 defined type

-1
votes

VHDL's floating point type (real) is not synthesizable (except perhaps by some very specialized tools), so if you have an input std_logic_vector in IEEE float form you will have to extract and process the required data fields (sign, exponent, mantissa) yourself (or use a library that does it for you, knowing the large amount of hardware resources this will consume).

Personally, I would avoid using floating point if at all possible, and stick to using fixed point instead.