Parameterized net width in Verilog

1
votes

Is something like this possible ?

parameter width; wire[width-1] a_net = (width)'b0;

I basically need a variable to control the width of the right hand side. I am planning to use this in an test bench where I just have to change the parameter width at the beginning of the file, and this parameter sets the net width in all other occurrences of 'a_net'.

If this doesn't work - is there any other workaround ?

Thanks, Jim

2
verilogfpgahdl

2 Answers

4
votes

In the example you could just use a localparam instead of a constant wire.

localparam ZERO = 'b0; // Syntax for RHS discussed below.

For RHS (right hand side) arguments you can use the replication operator.

{ WIDTH {1'b0}}; //Repeats 1'b0 WIDTH times.

All 1's

{ WIDTH {1'b1}};

For Max Signed (MSB == 0) mix Concatination and replication, both use {}

{1'b0, { WIDTH-1 { 1'b1 }} };

As of 2012 SystemVerilog can use '0 for 0 the same width as the left hand side. '1 All 1's.

1
votes

I think you need to specify the LSB of your wire as well:

parameter WIDTH = 16;

wire [WIDTH-1:0] a_net = 0;