Verilog - always sensitivity list

Question

I am looking to map the four basic operations (multiplication, addition, subtraction, and division) to one of four keys which are located on my FPGA board. I have an if-statement which would check to see which key is pressed and execute the appropriate statements. However, when writing the always block sensitivity list no matter what I place in the block it will not recognize all four keys. If I leave the sensitivity block empty then it will recognize all of the keys but will perform the operation of the first key and wait for the other keys to be pressed to perform those operations.

always @(negedge KEY) begin
    if (KEY[0] == 0) begin
    ...
    end else if(KEY[1] == 0) begin
        //Check for value for A and B
        if(SW[15:8] < SW[7:0]) begin
            ...     
        end
    end else if(KEY[2] == 0) begin
    ...
    end
end

Implementing the code like this will calculate only the operation which is connected to KEY1. The rest of the keys act as if they have not been programmed. Is there any way around this small annoyance?

Thanks!

Tim Tim · Accepted Answer · 2013-05-01T03:18:28

Unless you're modelling a clocked flip flop, you should always use the default (@*) sensitivity list for a combinational block. There's no synthesizable combinational circuit which is only sensitive to the negative edge of a signal.

If you really want to do something only when a key is initially pressed, then compare the key state to the value of the key from the previous clock edge stored in a register.

always @* begin
  if(key[0] && !key_last[0]) begin
      //assert some signal on key0 press
  end
  if(key[1] ...) begin
      //assert on key1 press
  end
end

always @(posedge clock) key_last <= key;

If you intend to check the state of more than one key, then you shouldn't use if/else statement, as that will stop checking after the first true statement. Just write four individual if statements.

Verilog - always sensitivity list

2 Answers