VHDL RAM port map

Question

I have a ram entity and I want to access it from 2 different other entities A and B. I make entity port map inside both A and B, but when I start simulation on modelsim I get two rams one for entity A and one for entity B. WhatIi want is to have both entities access the same ram not separate rams for each entity. How to accomplish this using modelsim pe student edition?

Answer 1

As you have discovered, that is not the way to do it.

Create a top level entity that instantiates both entities A and B, create the RAM in there too (by whichever technique you prefer), and connect it via signals to the correct ports of A and B.