Difference in Clock Generation

Question

What is the difference between the following codes ?

initial begin
  clk = 0 ;
  forever begin
    #5  clk =   ~clk;
  end
end


initial begin
  clk = 0 ;
  forever begin
    clk = #5  ~clk;
  end
end

I do know the difference between Inertial and Transport Delays and I know that clock is generated in both the cases(with some Phase difference between the two ), but I want to know how the simulator reacts to the following codes.Is it the same or different ? Like how many events are taken into consideration while calculating the value ?

Morgan Morgan · Accepted Answer · 2013-04-02T11:55:59

The difference between the two from a usage point:

#5 clk = ~clk; means wait 5 time steps then execute clk = ~clk;

For Wires B = #5 A; means B is assigned to A from 5 timestep ago. A leads B by 5 timesteps. If B is changed to A A = #5 A;

wire B;
assign B= #5 A;

Usage for a wire is covered by the IEEE 1800-2012 section 6.7 Net declarations

From @new2androids update syntax A = #5 B;, for a registers is different from that of a wire. B is checked every 5 time units and A is assigned the value immediately. Which is why it works for testbench clock generation.

As to how the simulator reacts, there may be some standard scheduling practises that others can comment on but to a degree it may depend on the simulator you are using.

@new2android Provided the follwoing info read from 1996 : Understanding Verilog Blocking and Non--blocking Assignments

#5 A = B; Pulses with width less than 5 are ignored by the Simulator
A = #5 B; Input is checked every 5 time units and assigned the value immediately

Notes

All uses of delays are for simulation only and are not synthesizable.
The question & answer does not cover the differences when using non-blocking variants of the delays (B <= #5 A;, #5 B <= A;).

Difference in Clock Generation

1 Answers