What is the proper way to add delays to, eg. 74HCT151, verilog model so it is accurate to the datasheet?

Question

What is the proper way to add delays to this model of a 74hct151 - see below. See also my effort at a solution.

I would like to see even one fully accurate (as possible) verilog model of 7400 timings so I could understand the concerns and build my own. The 74151 is interesting because the Y and _Y paths have different times and also because it's the most recent one I've needed for my homebrew"TTL" cpu.

I am using Icarus so I need a solution for that. I don't have other tools and I know that some tools have bugs/quirks/missing features so something that works on a commercial tool but not Icarus is an issue.

I am hoping someone would show me a solution so I can learn.

I do have a solution below but I think it's probably bit pants.

I want a design that allows through realistic glitches.but my earlier attempts suppressed short glitches due to how I was doing delays. I believe this is called "transport delay" as opposed to "inertial delay".

As mentioned in the following document using transport delays is useful for finding glitch risks.. section 4.3 https://www.google.co.uk/url?sa=t&source=web&rct=j&url=http://cs.baylor.edu/~maurer/aida/desauto/chapter4.pdf&ved=2ahUKEwjYtpS06pHsAhUEXRUIHVtJAos4FBAWMAB6BAgAEAE&usg=AOvVaw1CUNhobqxQe-pQIEZiBKm_

With correct delays I am expecting to see a transition glitch on the Y/_Y during certain transitions due to the difference in the S and I propagation delay.

The data sheet says this chips glitches during transitions and this shows up in my best shot at the timings

These needed delays are taken from datasheet for HCT in ns
 I to  Y = 19
 I to _Y = 19
 S to  Y = 20
 S to _Y = 20
_E to  Y = 16
_E to _Y = 18
transition time Y, _Y = 7

See also https://assets.nexperia.com/documents/data-sheet/74HC_HCT151_Q100.pdf

The basic code below has no delays.

How do I implement correctly?

See edaplayground link above for my novice solution.

I expect there is a more idiomatic way to get these timings.

Here is the basic logic without delays....


`timescale 1ns/1ns

module hct74151(_E, I, S, Y, _Y);
    output Y, _Y;
    input [2:0] S;
    input [7:0] I;
    input _E;

    wire o =
        (S==0 & I[0]) ||
        (S==1 & I[1]) ||
        (S==2 & I[2]) ||
        (S==3 & I[3]) ||
        (S==4 & I[4]) ||
        (S==5 & I[5]) ||
        (S==6 & I[6]) ||
        (S==7 & I[7]);

    assign Y = _E==0 ? o : 0;
    assign _Y = !Y;

    always @* begin
        $display("%9t %m ", $time, "_E=%1b  I=%8b  S=%1d   Y=%b _Y=%b ", _E, I, S, Y, _Y);
    end

endmodule

:

I am using Icarus verilog btw. I don't believe this can be done with a specify block at least with Icarus. I want all glitches to come thru, not suppressed. But it seems that the left hand side approach for delays works like a low pass filter so fluctuations on the input that are shorter than the propagation delay are suppressed. However I want a model that works like a real chip, a worst case with glitches galore. — johnlon

Unknown Unknown · Accepted Answer · 2020-09-30T10:35:17

Here is my solution, but is it idiomatic? Is there a better way that works on icarus?


module hct74151(_E, I, S, Y, _Y);
    parameter LOG=0;
    output Y, _Y;
    input [2:0] S;
    input [7:0] I;
    input _E;

    // setup timing be delaying the signals according to the data PD then combine them at last minute
    logic [7:0] Id;
    logic [2:0] Sd;

    always @*
        Id <= #(19) I;

    always @*
        Sd <= #(20) S;

    // according to nexperia _E->_Y is slower than _E->Y
    logic _Ed, Ed;
    always @*
        _Ed <= #(13) _E;
    always @*
        Ed <= #(18) ! _E;

    // combine
    wire O =
        (Sd==0 & Id[0]) ||
        (Sd==1 & Id[1]) ||
        (Sd==2 & Id[2]) ||
        (Sd==3 & Id[3]) ||
        (Sd==4 & Id[4]) ||
        (Sd==5 & Id[5]) ||
        (Sd==6 & Id[6]) ||
        (Sd==7 & Id[7]);

    assign Y = _Ed==0 ? O : 0;
    assign _Y = Ed==1 ? !O : 1;

    if (LOG) always @*
    begin
        $display("%9t %m ", $time, "_E=%1b  I=%8b  S=%1d   Y=%b _Y=%b (_Ed=%b, Ed=%b)", _E, I, S, Y, _Y, _Ed, Ed);
    end

endmodule

What is the proper way to add delays to, eg. 74HCT151, verilog model so it is accurate to the datasheet?

1 Answers