How to access text files at synthesis level

Question

I am writing Verilog code using Lattice Diamond for synthesis.

I have binary data in a text file which I want to use as input for my code.

At simulation level we can use $readmemb function to do it. How is this done at synthesis level?

I want to access data present in text file as an input for FPGA.

As suggested by Mr Martin Thompson(answers below) I have written a Verilog code to read data from a file.

Verilog code is given below:-

module rom(clock,reset,o0);
 input clock,reset;
 output o0;
 reg ROM [0:0];
 reg o0;
 initial
  $readmemb("rom.txt",ROM);
 always @(negedge clock,negedge reset )
   begin
if(reset==0)
    begin
    o0<=0;
    end
else
    begin
    o0<=ROM[0];
    end
  end
endmodule

When I am running this code on fpga I am facing the problem below:-

If text file which I want to read have only one bit which is '1' then I am able to assign input output pins to clock,reset and ROM. But if I have one bit which is '0' or more than one bits data in text file I am unable to assign input pins(i.e clock,reset) and a warning is displayed:-

 WARNING: IO buffer missing for top level port clock...logic will be discarded.
 WARNING: IO buffer missing for top level port reset...logic will be discarded.

I am unable to understand why I am getting this warning and how I can resolve it.

Answer 1

One way is to build the data into the netlist that you have synthesised. You can initialise a read-only memory (ROM) with the data using $readmemb and then access that as a normal memory from within your device.

Here's an introduction to some memory initialisation methods:

http://myfpgablog.blogspot.co.uk/2011/12/memory-initialization-methods.html

And in here:

http://rijndael.ece.vt.edu/schaum/slides/ddii/lecture16.pdf

is an example of a file-initialised RAM on the second to last slide. If you want just a ROM, leave out the if (we) part.

Answer 2

Think of Simulation as an environment not a level. You should just be switching the DUT (Device Under Test) from the RTL code to the synthesised netlist, other than this nothing should change in your simulation environment.

From the block of code you have given it does not look like you are separating out the test and code for the fpga. You should not be trying to synthesise your test I would recommend splitting it between at least 2 separate modules, your test instantiating the code you want to place on the fpga. Pretty sure the $fwrite is also not synthesizable.

A simple test case might look like:

module testcase
  //Variables here
  reg reg_to_drive_data;

  thing_to_test DUT (
    .input_ports ( reg_to_drive_data )
    .output_ports ()
    ...
  ); 

  //Test
  initial begin
    #1ns;
    reg_to_drive_data = 0;
    ...
  end
endmodule

Via includes, incdir or file lists the code for thing_to_test (DUT) is being pulled in to the simulation, change this to point to the synthesised version.

If what you are trying to do is initialise a ROM, and hold this data in a synthesised design Martin Thompson's answer covers the correct usage of $readmemb for this.