PCIe interrupt routing

1
votes

I am currently implementing a PCIE endpoint device in xilinx PFGA, and have some problem regards to the interrupt.

when the driver init, it map the interrupt to IRQ 32

[ 1078.938669]   alloc irq_desc for 32 on node -1
[ 1078.938670]   alloc kstat_irqs on node -1
[ 1078.938675] pci 0000:06:00.0: PCI INT A -> GSI 32 (level, low) -> IRQ 32

However, when the interrupt fires, 

[ 1134.850064] irq 16: nobody cared (try booting with the "irqpoll" option)
[ 1134.850067] Pid: 0, comm: swapper Tainted: P           2.6.32-5-amd64 #1
[ 1134.850069] Call Trace:
[ 1134.850070]  <IRQ>  [<ffffffff81095d89>] ? __report_bad_irq+0x30/0x7d
                          .
                          .
                          .
[ 1134.850119] handlers:
[ 1134.850120] [<ffffffffa0e7935e>] (azx_interrupt+0x0/0x11d [snd_hda_intel])
[ 1134.850124] Disabling IRQ #16

The irq seems to be routed to to another pin IRQ #16. And I used the PCIe msi interrupt. What could cause this problem?

2
linuxinterruptfpgapci
Can you add the PCI config registers for this device? Specifically the int pin/line registers. – Chris Desjardins
What FPGA are you using? Is this a question for a MicroBlaze system or is it a Zynq question? Or does the FPGA act as the PCIe bridge for an external CPU? It will be helpful if you give us a bit more data about what you have so we get a hint of what might be the problem. – FarhadA
More details about your PCIE endpoint and kernel driver are required in order to answer the question. – Jamey Hicks

2 Answers

1
votes

I think u maybe using ML555 board. This is a website about PCIE driver on ML555. Luckily it's still alive. https://asim.csail.mit.edu/redmine/projects/leap-platforms/repository/show/trunk/drivers/linux/platforms/htg-pcie-virtex5/src I also meet some obstacle about driver of pcie device. So we can exchange about that.

1
votes

I've run into similar problems.

1) Chris said in his comment, make sure you implement the MSI registers in PCI configuration space. These registers are written by the BIOS/OS to tell the hardware what value to write to which address for the MSI interrupt.

2) Make sure that the PCIE endpoint (pcie_7x?) has the address of those registers configured. 4 registers are required per interrupt. The address given to coregen is a 16-bit word address.

Hope this helps.