PCIe JTAG for (re)programming a PCIe board

3
votes

I noticed that the PCI bus has the JTAG wires (i.e. TCK TDI TDO etc.): is there any way to use that JTAG for re-programming an fpga based PCIe device? (supposing that the fpga's JTAG is connected to the PCI wires).

thanks Michele

EDIT: since I see a -1, maybe I couldn't make myself understood... I'm going to try to better explain the situation. We have a Terasic DE5 (Stratix V FPGA) PCIe board, which actually has the JTAG "wires" of the PCIe bus routed to the FPGA. It's true that there is a JTAG port soldered on the board, but for mechanical reasons is hard to reach and use. So my question is: is it possible to use the PCI pins to programm the FPGA as we can do with the BLASTER? if so, what's the linux infrastructure to support the PCIe JTAG programming? If there's no chance, could someone explain me why?

2
fpgapcipci-e
Maybe? Can a JTAG programmer detect the FPGA in the JTAG chain? This it totally board-dependent. – Russell
ok, but what's the software infrastructure provided by Linux? is there any primitive/component (maybe subsystem?) used to "control" the PCIe JTAG? – Michele
It might be possible. If the Flash can be visible to the PCI address space you can do this. I looked over the User Manual and didn't see anything that indicated if this was possible. This sounds like a question for Terasic. – Russell

2 Answers

1
votes

I've never come across any motherboard which allows the host processor access to the JTAG on the PCI slots. It's there (as I understand it) for manufacturers to use in end-of-line test kit.

I guess you might find some JTAG pins on a header somewhere. Again, I've never come across any motherboard with that documented for end users.

1
votes

I've looked at the JTAG connections you describe but found no way to use them. These connections seem to be only useful for manufacturing test of a motherboard with FPGA board attached. That is the purpose for which JTAG (boundary scan) was original designed.

Here are two alternatives to what you propose:

  1. Send new bitstreams over PCIe, write them to the boot flash. Reset the FPGA to load the new design. On some machines, you can reset the FPGA without rebooting by requesting Linux to rescan the device.

  2. Send new bitstream over PCIe, and use partial reconfiguration to load the changed part of the design. This requires an additional license from Altera.