where can I find a description of *all* MIPS instructions

Question

Does anyone know of a web site where I can find a list of 32-bit MIPS instructions/opcodes, with the following features:

• Clearly distinguishes between real opcodes and assembly-language macros (pseudo-instructions)
• Describes the instruction behavior including differences depending on privilege level.
• Indicates in which instruction set revision the instruction was introduced/revised (e.g. MIPS I, MIPS II, MIPS32, etc.)
• Includes privileged instructions such as syscall.

I am aware of numerous web sites which document "part of" the instruction set, mostly for teaching purposes. They tend to leave out or only partially describe floating-point and privileged instructions.

In case you're wondering, I'm looking at Verilog code for a MIPS processor subset, and trying to figure out exactly to what extent it complies with the instruction sets of any real MIPS processors!

Answer 1

I can only partially answer the question: I'd recommend See MIPS Run by Dominic Sweetman, if you're not already referring to it. I have the first edition of the book, the second edition is now current.

• table 8.2 lists each opcode and expected behavior, differentiating assembler macros and listing the instructions they decompose to. Unfortunately it does not differentiate user vs kernel mode.
• table 8.6 lists the ISA level where each instruction was introduced, including obscure variants like the LSI MiniRISC
• syscall is present in the table, though lacking much description

The first edition mentions the kernel. supervisor, and user privilege levels but does not discuss what operations are allowed in each. I do not know what changes were made in the second edition.

Answer 2

Okay, I found something!

MIPS offers a set of "MIPS 32 reference manuals" which refer to the latest, standardized instruction set (MIPS32v2): here

These include just about everything, except the information about which version the instructions originated in :-(

WAIT A SEC...

This class website at Cornell includes links to what appears to be the same manual, but is in fact an older version of it, and volume 2 of that older version does in fact include information about when the instructions where first introduced. Woohoo!

Why would MIPS remove this information from the revised documentation? There doesn't seem to be any explanation in the revision history.

Answer 3

Doesn't include instruction descriptions, but the source of the GNU assembler is probably as detailed as you can get regarding what instructions are available on what specific CPUs.

Get binutils and look at opcodes/mips-*.c

Answer 4

The current instruction-set reference manual is free online: MIPS® Architecture for Programmers Volume II-A: The MIPS32® Instruction Set Manual. That link is Revision 6.06 December 15, 2016. (i.e. it documents MIPS32 Release 6).

It documents all user and supervisor/kernel mode instructions, and all floating-point, in full detail including their machine-code encoding, and with an Operation section that shows what they do. It still documents all the instructions that were removed in MIPS32 release 6. (MIPS32 Release 6 also moved around a lot of opcodes, and this is well documented).

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See https://www.mips.com/products/architectures/mips32/ for the latest version. mips.com has a section for "classic cores", but that still appears to only go back to MIPS32, not historical stuff.

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Sample of the "availability and compatibility" section for balc (Branch and Link Compact: no branch-delay slot, and GRP31 is the implicit destination, freeing up 26 bits for an offset<<2):

This instruction is introduced by and required as of Release 6. Release 6 instruction BALC occupies the same encoding as pre-Release 6 instruction SWC2. The SWC2 instruction has been moved to the COP2 major opcode in MIPS Release 6

Or for LDXC1 fd, index(base) (Load Doubleword Indexed to Floating Point)

This instruction has been removed in Release 6. Required in all versions of MIPS64 since MIPS64 Release 1. Not available in MIPS32 Release 1. Required in MIPS32 Release 2 and all subsequent versions of MIPS32. When required, required whenever FPU is present, whether a 32-bit or 64-bit FPU, whether in 32-bit or 64-bit FP Register Mode (FIRF64=0 or 1, StatusFR=0 or 1).

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For historical stuff, I found the MIPS IV Instruction Set Revision 3.2 September, 1995 on a cmu.edu web page. It lists when instructions were introduced, e.g. MIPS I for div, MIPS III for dmult and other 64-bit instructions, MIPS II for ll / sc.

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A good quick-reference with pseudocode for the effect of each instruction is https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_help.html. It doesn't include encoding details, but does accurately describe the effect of branch and jump instructions on the program counter. (Which is somewhat tricky: they're relative or section-absolute to the branch-delay slot.)

It's not complete even for MIPS I integer instructions, though: it's missing the unaligned-load helper instructions LWL and LWR and corresponding SWL/R stores which were present in MIPS I. It also doesn't include any FP stuff, or later MIPS instructions like mul (only mult). I don't know what else might be missing; I didn't cross reference it against a complete list.

The MIPS-IV manual linked above confirms that lwl/lwr were available in MIPS I (and documents that the load delay slot restriction applies to them).

Answer 5

This web site (archive.org) describes most of the MIPS instruction set and their encoding. It's not complete, though: missing at least nor and maybe other things.

A good quick-reference with pseudocode for the effect of each instruction is https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_help.html. It doesn't include encoding details.

The MIPS web site also has technical documents about the various cores.
For example, I downloaded the manual for the MIPS 4KE core (document #MD00103) "MIPS32® 4KE™ Processor Core Family Software User’s Manual" and chapter 10 contains a detailed description of the Instruction Set. Note that you have to register to access the documents.