VHDL filtering data

Question

I am new to VHDL. I need to write a module to do filtering of data. My module structure is:

a_rst - async reset
clk - clock
s_rst - sync reset
valid_in - 0 - no data, 1 - where is data
data_in - [7 downto 0]

Out signals:

valid_out - 0 - no data, 1 - where is data
data_out - [7 downto 0]

I write testbeanch which puts to data_in of my module: 00,01,02,03,0A,02,00,01,02,0F.

But my module returns: 00,01,AA,03,0A,02,00,01,AA,0F
insted of: 00,01,AA,03,0A,02,00,01,02,0F.

I tried to do this:

--libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--entity
entity ex6_v03 is
port
(
a_rst     : in std_logic;
clk       : in std_logic;  -- 200 MHz
s_rst     : in std_logic;
valid_in  : in std_logic;
data_in   : in std_logic_vector (7 downto 0);
valid_out : out std_logic;
data_out  : out std_logic_vector (7 downto 0) 
);
end entity ex6_v03;


architecture behavior of ex6_v03 is

signal st : integer := 0;

begin

process(a_rst, clk)
begin
-- asynchronous reset
if (a_rst = '1') then
 data_out <= x"00";
 valid_out <= '0';

-- synchronous reset        
elsif rising_edge(clk) then -- clk
  if (s_rst = '1') then
    valid_out <= '0';
    data_out <= x"00";     
  else                             
    -- normal activity
    if(valid_in = '1') then
      -- main logic
      if(data_in = x"00") then
        st <= 1;
        valid_out <= '1';
        data_out <= data_in;
      elsif(st = 1 and data_in = x"01") then
        st <= 2;
        valid_out <= '1';
        data_out <= data_in;
      elsif(st = 2 and data_in = x"02") then
        st <= 3; 
        valid_out <= '1';
        data_out <= x"AA";
      elsif(st = 3 and data_in = x"03") then
        valid_out <= '1';
        data_out <= data_in;
        st <= 0; 
      else
        st <= 0;
        valid_out <= '1';
        data_out <= data_in;
      end if;

      -- end main logic
    else
      valid_out <= '0';
      data_out <= x"00";   
    end if; 
  end if;
end if;
end process;

end architecture behavior;

But my module do not wait for 0x03 and instantly sends 0xAA. How to fix this?

How to add buffering to this? When in input meet 00,01,02,03 replace by 00,01,AA,03. — John Smith
do you mean, substitute AA for O2, but only when the next state is 03? Or only in the sequence 01, 02, 03? Or in the sequence 00, 01, 02, 03? or only the first occurrence of 02 but no others, or .... you CANNOT possibly get a sensible answer until you ask a sensible question. — user_1818839
Then you cannot decide what to send for state N, until you know the input value for state N+1. — user_1818839

QuantumRipple QuantumRipple · Accepted Answer · 2013-10-07T04:11:29

You need to add a 1 clock cycle buffer so you know if the next input is 03 before you choose whether to send 02 or AA. Of course, this means the output wont appear until 2 cycles after the input instead of only one. See revised code:

--libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--entity
entity ex6_v03 is
port
(
a_rst     : in std_logic;
clk       : in std_logic;  -- 200 MHz
s_rst     : in std_logic;
valid_in  : in std_logic;
data_in   : in std_logic_vector (7 downto 0);
valid_out : out std_logic;
data_out  : out std_logic_vector (7 downto 0) 
);
end entity ex6_v03;


architecture behavior of ex6_v03 is

signal st : integer := 0;
signal bvalid : std_logic := '0'; --is buffer valid?
signal data_buffer : std_logic_vector (7 downto 0); --data from previous cycle

begin

process(a_rst, clk)
begin
if (a_rst = '1') then -- asynchronous reset
 data_out <= x"00";
 valid_out <= '0';
 bvalid <= '0';

elsif rising_edge(clk) then -- clk
  if (s_rst = '1') then --sync reset
    valid_out <= '0';
    bvalid <= '0';
    data_out <= x"00";     
  else -- normal activity  

    if(valid_in = '1') then --fill buffer

      if(data_in = x"00") then
        st <= 1;
        data_out <= data_in;
      elsif(st = 1 and data_in = x"01") then
        st <= 2;
        data_out <= data_in;
      elsif(st = 2 and data_in = x"02") then
        st <= 3; 
      else
        st <= 0;
      end if;  

      data_buffer <= data_in;
      bvalid <= '1';
    else
      bvalid <= '0';   
    end if; 

    if(bvalid = '1') then --use buffer to populate output
        valid_out <= '1'
        if(st = 3 and data_in = x"03" and valid_in = '1') then --EDIT: make sure the x"03" sitting on the input is actually valid
          data_out <= x"AA"; --output for the previous cycle (buffer contains x"02")
        else
          data_out <= data_buffer;
        end if
    else
      valid_out <= '0';
      data_out <= x"00";
    end if;

  end if;
end if;
end process;

end architecture behavior;

VHDL filtering data

1 Answers