Shared variable in VHDL

Question

I'm new in vhdl (with ISE project navigator) and I'm having a little problem to synthesize this program (sequence.vhd):

LIBRARY ieee ;
USE ieee.std_logic_1164.all;

PACKAGE mypack IS
VARIABLE counter: STD_LOGIC := '0' ;
VARIABLE simultaneous : STD_LOGIC := '0' ;
END PACKAGE mypack;

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;


--library work;

USE WORK.mypack.ALL;

ENTITY secuencia IS

PORT(
    polh            : IN    STD_LOGIC; --uno
    polv            : IN    STD_LOGIC; --cero
    seq            : OUT   std_logic_vector(8 downto 0):= (others => 'Z')
);

END secuencia;


ARCHITECTURE registro OF secuencia IS

SIGNAL stack : std_logic_vector(1000 downto 0);


BEGIN
PROCESS(polh, polv)
 BEGIN

        IF (polh'event) and (polh='1') and (polv='0')THEN
            stack(counter) <= '1';
            counter := counter +1;

        ELSE IF (polv'event) and (polv='1') and (polh='0')THEN
            stack(counter) <= '0';
            counter := counter +1;
        ELSE IF (polh'event) and (polh='1') and (polv'event) and 
(polv='1') THEN
            simultaneous := simultaneous+1;

        END IF;

END PROCESS;

END registro;

And these are the first two errors:

Line 5. Only SHARED variables can be declared here.

Line 6. Only SHARED variables can be declared here.

So the problem is with my declared variables... The purpose is use them in the architecture. I'm sure is a newbie problem but I can't see the solutions. Thx a lot!

PD: I couldn't format properly the code, sorry

UPDATE:

Thx for helping @Martin Thompson . I did what you suggested and now im having a different type or problem. I've been searching about it but it seems to have a broad range of causatives. Here it is the code

ENTITY secuencia IS
PORT(
    polh            : IN    STD_LOGIC; --uno
    polv            : IN    STD_LOGIC; --cero
    Pedido      : IN    STD_LOGIC; 
    DatoListo   : OUT    STD_LOGIC; 
    seq            : OUT   std_logic_vector(1000 downto 0):= (others =>   'Z')

);
END secuencia;


ARCHITECTURE registro OF secuencia IS

SIGNAL stack : std_logic_vector(1000 downto 0);


BEGIN

PROCESS(polh, polv, Pedido) 

variable counteria : natural;
 variable Listo : integer;
 variable simultaneo : integer;
 BEGIN
    IF (counteria < 1000) THEN

       IF (polh'event AND polh='1' AND polv='0') THEN
        --IF (polh='1' AND polv='0') THEN
            stack(counteria) <= '1';
            counteria := counteria +1;


         ELSIF (polv'event AND polv='1' AND polh='0') THEN
         --ELSIF (polv='1' AND polh='0') THEN    
                stack(counteria) <= '0';
                counteria := counteria +1;                 

        ELSIF (polh'event AND polh='1' AND polv'event AND polv='1') THEN
           simultaneo := simultaneo+1;

END IF;

    ELSIF (counteria = 1000)THEN
      DatoListo <='1';
          IF (Pedido='1')THEN
               Seq  <= stack;            
           counteria := 0;
       DatoListo <='0';
            END IF;                                 
    END IF;

END PROCESS;
END registro;

and it gives this error

line 25: Signal stack> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

UPDATE 2:

I have make some changes and commenting a part of the program, it synthesize:

PROCESS(polh, polv, Pedido) 

     variable counteria : natural := 0;
     variable Listo : integer;
     variable simultaneo : integer;
 BEGIN
    IF (counteria < 1000) THEN
       IF rising_edge(polh) THEN
            IF (polv='0') THEN
               stack(counteria) <= '1';     
               counteria := counteria + 1;
            END IF;
--     ELSIF rising_edge(polv)  THEN
--          IF (polh='0') THEN
--             stack(counteria) <= '0';
--             counteria := counteria +1;                  
--          END IF;
--     END IF;

       ELSIF (counteria = 1000)THEN
           DatoListo <='1';
              IF (Pedido='1')THEN
                  Seq   <= stack;            
           counteria := 0;
           DatoListo <='0';
       ENDIF;                                           

    END IF;

END PROCESS;
END registro;

This Synthesize. However when I uncomment the ELSIF rising_edge(polv) THEN part, it presents the same problem: Signal stack<counteria<9:0>> cannot be synthesized...

Martin Thompson Martin Thompson · Accepted Answer · 2012-09-12T15:48:25

Don't use shared variables for now. You need to understand some basics first.

If you need to "send" the value of counter out to somewhere else, add an item to the port and write it to there.

If (as it appears) you just want to use it as storage, declare it within the process you use it within.

Finally, if you hope to synthesize this, you need to have a clock signal coming in through the port and you need to make a standard clocked process:

If you want to find when your polh and polv inputs change, you have to store the previous value and check if it's different to the current value.

process (clk)
    variable vpol_last : std_logic;
begin
  if rising_edge(clk) then
       if vpol_last /= vpol then -- it's changed
       -- do something
       end if;
       vpol_last := vpol; -- store current value for next time.
       -- etc.
  end if;
end process;

Shared variable in VHDL

1 Answers