Xilinx True Dual Ported RAM with different aspect ratios on two ports

1
votes

I am trying to build a RAM block in Verilog with the following configuration:

  • Port A: 128 bit wide, with clk_a, sees RAM block as 128 bit wide times 128 lines deep
  • Port B: 32 bit wide with clk_b, sees RAM block as 32 bit wide times 512 lines deep

Do not worry about READ-WRITE serialization and mutexing, I will be taking care of it with a layer above that.

Basically, the code that generates the 128 bit times 128 lines looks like:

reg [DATA_WIDTH-1:0]                 mem  [0:2**ADDRESS_WIDTH-1];

Now, if I want it to look like 32 bit times 512 deep, how do I refactor this memory to look different (kind of like a recast in C) ? I understand that I might be able to do this with 32 bit word enable(s), but I am trying to see if there is a cleaner way to achieve this.

Let me know what you think ?

RRS

Correction: I am referring Xilinx BRAM (BRAMs cant be 512 deep). But this is essentially a memory block with the glue logic chaining multiple BRAMs. Thanks for pointing out !!

2
vhdlverilogramfpgaxilinx
You realise that a Xilinx BRAM cannot be less than 512 words deep? In other words, a 128-bit wide RAM requires at least ceil(128/36) = 4 BRAMs. - Oliver Charlesworth
I call it a Xilinx BRAM (but it is essentially an inferred memory block). I would let XST figure out the glue logic. My Bad with the definitions :-( - boffin
No worries, I wasn't trying to correct your definitions! I was just pointing out that you can't magically get a 128x128 RAM in the same resource footprint as a 32x512. - Oliver Charlesworth
Certainly footprints will be different. At this point I am not too worried about area, I am worried about functionality and cleanliness. - boffin
I'm a bit unclear on if you actually want to use the embedded BlockRam blocks, and Xilinx may have changed the functionality in ISE 13, but in ISE 12 at least, it isn't possible to infer true dual port blockram with different aspect ratios - you'll need to instantiate them through for instance CoreGen. Reference: forums.xilinx.com/t5/Synthesis/… - sonicwave

2 Answers

2
votes

I solved it this way:

In ISE, I was able to find "Language Templates" in one of the menus which has actual code samples. There is one with "File I/O", that one works perfectly.

You can also build a wrapper module around the dual port RAM which will change data widths on the other side. On the smaller data-width port (i.e. more address lines) you can use the lower address bits as a word select system allowing you to write to part of a memory line. This synthesizes properly for me (check your synthesis tool).

0
votes

For instructions on exactly how to do this, see the Xilinx documentation. For example, http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/xst_v6s6.pdf starting at page 217 gives explicit VHDL and Verilog examples of how to do what you are asking.