Verilog: Difference between `always` and `always @*`

Question

Is there a difference between an always block, and an always @* block?

Answer 1

always @* is one type of always block. It is used for inferring combinational logic.

always @(posedge clock) is used to infer sequential logic.

Refer to the IEEE Standard (1800-2009, for example) for further details.

Answer 2

They are different! I used to think they were the same. But it is not.

always @(*) means sense anything, compiler would fill it auto. If it is a combination logic, use it! So you won't forget anything and make the function fail.

always means it is sentence would be always executed! If no delay in it, system halted and no result would be get when you simulation! Very annoying.

For example, in FSM's next state logic part: if use always instead of always @(*), it doesn't work.

Following is a simple sequence detector I wrote, where these two different. You could write a tb to run it if want.

`timescale 1ns/10ps

module seq_detect3( //detect sequence 10110 in, //sequence input clk, //clock positive edge trigged rst, //reset, active-high synchronous match //out match, "1" for matched );

input in, clk, rst;
output match;
wire in, clk, rst;
reg match;
reg [5:0] state, next_state;
parameter IDLE = 6'b000001;     //no bit matched
parameter STATE1 = 6'b000010;   //first 1 bit matched
parameter STATE2 = 6'b000100;   //first 2 bits matched
parameter STATE3 = 6'b001000;   //first 3 bits matched
parameter STATE4 = 6'b010000;   //first 4 bits matched
parameter STATE5 = 6'b100000;   //all 5 bits matched

//-----------S.M. & O.F.L.-----------
always @ (posedge clk) begin
    if(rst) begin
        state <= IDLE;
        match <= #1 0;
    end
    else begin
        state <= next_state;
        if(state == STATE5) begin
        match <= #1 1;
        end
        else begin
            match <= #1 0;
        end
    end
end 

//-----------next state logic-----------
always @(*) begin    //Can not replaced by always here!!
    case(state)
        IDLE:   if(in) next_state = STATE1; //0 keep, 1 next
                        else next_state = IDLE; 
        STATE1: if(in) next_state = STATE1; //0 next, 1 keep
                        else next_state = STATE2;
        STATE2: if(in) next_state = STATE3; //0 idle, 1 next
                        else next_state = IDLE;
        STATE3: if(in) next_state = STATE4; //0 s2, 1 next
                        else next_state = STATE2;   
        STATE4: if(in) next_state = STATE1; //0 next, 1 s1
                        else next_state = STATE5;
        STATE5: if(in) next_state = STATE3; //0 idle, 1 s3
                        else next_state = IDLE;
        default: next_state = IDLE;
    endcase
end

endmodule