In a makefile, can I call a rule from another rule?
Similar to:
rule1:
echo "bye"
rule2:
date
rule3:
@echo "hello"
rule1
Either use dependencies or recursive making to connect from one rule to another.
Dependencies would be done like this (though the order will be different):
rule1:
echo "bye"
rule2:
date
rule3: rule1
@echo "hello"
Recursive make would be done like this (though it does involve a subprocess):
rule1:
echo "bye"
rule2:
date
rule3:
@echo "hello"
$(MAKE) rule1
Neither is perfect; indeed, with recursive make you can get into significant problems if you build a loop. You also probably ought to add a .PHONY
rule so as to mark those rules above as synthetic, so that a stray rule1
(etc.) in the directory won't cause confusion.
There are two advanced functions in GNU Make which can do this, although it should only be used in extenuating circumstances. This SO is top rated in google.
Rule prerequisites are more recommended, but sometimes you need a post-requisite.
Essentially, Eval lets you build targets on the fly, and Call allows function like "defines" to be created.