Modern superscalar processors generally make instruction execution appear to be completely deterministic and in-order from the perspective of something outside of the CPU. Internally, it's fetching instructions ahead, executing instructions speculatively, and executing them in whatever order is most efficient. But anything that shouldn't have been executed (e.g. mispredicted branch) doesn't get committed, and memory accesses are generally put back into the right order before leaving the CPU. The tail-end of a CPU pipeline is called the "re-order buffer" because it's job is to track completing instructions and only permanently commit their results in program order. This is important for proper program behavior, particularly in the face of things like branch misprediction and exceptions; if an exception occurs (e.g. divide by zero), subsequent instructions may have been decoded and executed, and these have to be purged from the ROB and program counter reset properly before handing the exception off to the OS.
With regard to memory ordering, there are some exceptions to the illusion of program ordering, where reads can get reordered arbitrarily, and there can be some (possibly speculative) reordering between reads and writes, but you only care about that when talking to memory-mapped I/O hardware. There are instructions that ensure a particular ordering, and CPUs are very careful with the ordering of accesses to un-cached memory, because that's assumed to mean it's I/O.
