Beginner's Question on Compiling Verilog in Quartus

Question

I'm in the process of learning Verilog. I am trying to create a code where I get an LED to blink at a certain frequency. I know the clock I am using is 100Mhz, so I wanted it to operate at a cycle of 1Hz. I set a registry for 27 bits, which should get me to the 1*10^8.

module main(
        input wire clk,         //100MHz//
        input wire reset_,
        output reg[1:0] LED1        //LED On/Off Two-States//
        );
        reg ON = 1'b1;      //INIT//
        reg[27:0] LEDStateCount;    //LED Counter - 27 Bit Stored//
        reg OFF;            //State of LED//
    
        assign LED1[0] = OFF;       
        assign LED1[1] = ON;
    
        always @(posedge clk or negedge reset_)begin
            if (!reset_)begin
                LEDStateCount <= 27'd0;    //On startup, clear value//
            end
            else if (LEDStateCount<LEDStateCount[27'd50000000])begin
                LEDStateCount <= LEDStateCount + 1;             //Accumulate to ~50,000,000//
                OFF <= LEDStateCount[27'd50000000];             //LED Off Until Value Reached//
            end
        end
    endmodule

I am getting an error when compiling in Quartus-

Error (10219): Verilog HDL Continuous Assignment error at Frequencytest.v(10): object "LED1" on left-hand side of assignment must have a net type

Error (10219): Verilog HDL Continuous Assignment error at Frequencytest.v(11): object "LED1" on left-hand side of assignment must have a net type

I believe it has something to do with what I declared when making my reg entries. These were two pages I used for reference when making this,

Badprog.com - LED Blinking In Verilog

Similar Thread with Blinking LED's

I'm sure there are other issues with this code other than those few syntax errors.

toolic toolic · Accepted Answer · 2021-10-19T15:18:09

The errors tell you that you should not use assign for reg types. To fix that, change:

    output reg[1:0] LED1        //LED On/Off Two-States//

to:

    output [1:0] LED1        //LED On/Off Two-States//

I also get warnings on both usages of LEDStateCount[27'd50000000].

Warning-[SIOB] Select index out of bounds
"LEDStateCount[27'd50000000]"
  The select index is out of declared bounds : [27:0].
  In module : main.

The number between the brackets must be between 0 and 27. It must not be 50,000,000.

        else if (LEDStateCount<LEDStateCount[27'd50000000])begin

should probably be something like:

        else if (LEDStateCount<27'd50000000)begin

Beginner's Question on Compiling Verilog in Quartus

1 Answers