I am trying to add a custom memory-mapped component in intel FPGA based soc system. I have connected the custom component(NVDLA) with light-weight axi bridge (HPS to FPGA bridge). Device Tree File.
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
model = "Terasic HAN Pilot (Arria 10 SX) ";
compatible = "altr,socfpga-arria10", "altr,socfpga";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
enable-method = "altr,socfpga-a10-smp";
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <0x1>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
next-level-cache = <0x1>;
};
};
intc@ffffd000 {
compatible = "arm,cortex-a9-gic-20.1", "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xffffd000 0x1000 0xffffc100 0x100>;
phandle = <0x2>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
nvdla_mem: buffer@0x40000000 {
no-map ;
reg = <0x0 0x40000000 0x0 0x40000000>;
};
};
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
device_type = "soc";
interrupt-parent = <0x2>;
ranges;
arria10_hps_bridges: bridge@0xff200000 {
compatible = "simple-bus";
reg = <0xff200000 0x00200000>;
clocks = <0x2c 0x2c>;
clock-names = "h2f_lw_axi_clock", "f2sdram0_clock";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x00000001 0x00000000 0xff200000 0x00040000>;
NVDLA_IP_0: nvdla@0x100000000 {
compatible = "nvidia,nv_small";
reg = <0x00000001 0x00000000 0x00040000>;
interrupt-parent = <0x2>;
interrupts = <0 19 4>;
clocks = <0x2c 0x2c 0x2c>;
clock-names = "clock", "dla_core_clock", "dla_csb_clock";
memory-region = <&nvdla_mem>;
}; //end unknown@0x100000000 (NVDLA_IP_0)
}; //end bridge@0xff200000 (arria10_hps_bridges)
amba {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
pdma@ffda1000 {
compatible = "arm,pl330-20.1", "arm,pl330", "arm,primecell";
reg = <0xffda1000 0x1000>;
interrupts = <0x0 0x53 0x4 0x0 0x54 0x4 0x0 0x55 0x4 0x0 0x56 0x4 0x0 0x57 0x4 0x0 0x58 0x4 0x0 0x59 0x4 0x0 0x5a 0x4 0x0 0x5b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x20>;
clocks = <0x3>;
clock-names = "apb_pclk";
microcode-cached;
phandle = <0x1e>;
};
};
clkmgr@ffd04000 {
compatible = "altr,clk-mgr-20.1", "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
clocks {
#address-cells = <0x1>;
#size-cells = <0x0>;
clk_100 {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x5f5e100>;
clock-output-names = "clk_100-clk";
phandle = <0x2c>;
};
clk_50 {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x2faf080>;
clock-output-names = "clk_50-clk";
};
cb_intosc_hs_div2_clk {
#clock-cells = <0x0>;
compatible = "fixed-clock";
phandle = <0xd>;
};
cb_intosc_ls_clk {
#clock-cells = <0x0>;
compatible = "fixed-clock";
phandle = <0x6>;
};
f2s_free_clk {
#clock-cells = <0x0>;
clock-frequency = <0x2faf080>;
compatible = "fixed-clock";
phandle = <0x7>;
};
osc1 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x17d7840>;
phandle = <0x5>;
};
main_pll@40 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-pll-clock";
clocks = <0x5 0x6 0x7>;
reg = <0x40>;
phandle = <0x8>;
main_mpu_base_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
div-reg = <0x140 0x0 0xb>;
phandle = <0xb>;
};
main_noc_base_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
div-reg = <0x144 0x0 0xb>;
phandle = <0xe>;
};
main_emaca_clk@68 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
reg = <0x68>;
phandle = <0x2d>;
};
main_emacb_clk@6c {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
reg = <0x6c>;
phandle = <0x2e>;
};
main_emac_ptp_clk@70 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
reg = <0x70>;
phandle = <0x2f>;
};
main_gpio_db_clk@74 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
reg = <0x74>;
phandle = <0x30>;
};
main_sdmmc_clk@78 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
reg = <0x78>;
phandle = <0x12>;
};
main_s2f_usr0_clk@7c {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
reg = <0x7c>;
phandle = <0x31>;
};
main_s2f_usr1_clk@80 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
reg = <0x80>;
phandle = <0x10>;
};
main_hmc_pll_ref_clk@84 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
reg = <0x84>;
phandle = <0x32>;
};
main_periph_ref_clk@9c {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x8>;
reg = <0x9c>;
phandle = <0x9>;
};
};
periph_pll@c0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-pll-clock";
clocks = <0x5 0x6 0x7 0x9>;
reg = <0xc0>;
phandle = <0xa>;
peri_mpu_base_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
div-reg = <0x140 0x10 0xb>;
phandle = <0xc>;
};
peri_noc_base_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
div-reg = <0x144 0x10 0xb>;
phandle = <0xf>;
};
peri_emaca_clk@e8 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
reg = <0xe8>;
phandle = <0x33>;
};
peri_emacb_clk@ec {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
reg = <0xec>;
phandle = <0x34>;
};
peri_emac_ptp_clk@f0 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
reg = <0xf0>;
phandle = <0x35>;
};
peri_gpio_db_clk@f4 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
reg = <0xf4>;
phandle = <0x36>;
};
peri_sdmmc_clk@f8 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
reg = <0xf8>;
phandle = <0x13>;
};
peri_s2f_usr0_clk@fc {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
reg = <0xfc>;
phandle = <0x37>;
};
peri_s2f_usr1_clk@100 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
reg = <0x100>;
phandle = <0x11>;
};
peri_hmc_pll_ref_clk@104 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xa>;
reg = <0x104>;
phandle = <0x38>;
};
};
mpu_free_clk@60 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xb 0xc 0x5 0xd 0x7>;
reg = <0x60>;
phandle = <0x15>;
};
noc_free_clk@64 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0xe 0xf 0x5 0xd 0x7>;
reg = <0x64>;
phandle = <0x14>;
};
s2f_user1_free_clk@104 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x10 0x11 0x5 0xd 0x7>;
reg = <0x104>;
phandle = <0x39>;
};
sdmmc_free_clk@f8 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x12 0x13 0x5 0xd 0x7>;
fixed-divider = <0x4>;
reg = <0xf8>;
phandle = <0x16>;
};
l4_sys_free_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <0x14>;
fixed-divider = <0x4>;
phandle = <0x29>;
};
l4_main_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x14>;
div-reg = <0xa8 0x0 0x2>;
clk-gate = <0x48 0x1>;
phandle = <0x3>;
};
l4_mp_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x14>;
div-reg = <0xa8 0x8 0x2>;
clk-gate = <0x48 0x2>;
phandle = <0x17>;
};
l4_sp_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x14>;
div-reg = <0xa8 0x10 0x2>;
clk-gate = <0x48 0x3>;
phandle = <0x1c>;
};
mpu_periph_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x15>;
fixed-divider = <0x4>;
clk-gate = <0x48 0x0>;
phandle = <0x28>;
};
sdmmc_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x16>;
clk-gate = <0xc8 0x5>;
clk-phase = <0x0 0x87>;
phandle = <0x20>;
};
qspi_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x3>;
clk-gate = <0xc8 0xb>;
phandle = <0x27>;
};
nand_x_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x17>;
clk-gate = <0xc8 0xa>;
phandle = <0x18>;
};
nand_ecc_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x18>;
clk-gate = <0xc8 0xa>;
phandle = <0x22>;
};
nand_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x18>;
fixed-divider = <0x4>;
clk-gate = <0xc8 0xa>;
phandle = <0x21>;
};
spi_m_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x3>;
clk-gate = <0xc8 0x9>;
phandle = <0x1d>;
};
usb_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x17>;
clk-gate = <0xc8 0x8>;
phandle = <0x2a>;
};
s2f_usr1_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <0x11>;
clk-gate = <0xc8 0x6>;
phandle = <0x3a>;
};
};
};
stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <0x0 0x0 0x0 0x0 0x10 0x0 0x0>;
phandle = <0x1b>;
};
ethernet@ff800000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
altr,sysmgr-syscon = <0x19 0x44 0x0>;
reg = <0xff800000 0x2000>;
interrupts = <0x0 0x5c 0x4>;
interrupt-names = "macirq";
mac-address = [d6 7d ae b3 0e bc];
snps,multicast-filter-bins = <0x100>;
snps,perfect-filter-entries = <0x80>;
tx-fifo-depth = <0x1000>;
rx-fifo-depth = <0x4000>;
clocks = <0x17>;
clock-names = "stmmaceth";
resets = <0x1a 0x20>;
reset-names = "stmmaceth";
snps,axi-config = <0x1b>;
status = "okay";
phy-mode = "rgmii";
phy-addr = <0xffffffff>;
txd0-skew-ps = <0x0>;
txd1-skew-ps = <0x0>;
txd2-skew-ps = <0x0>;
txd3-skew-ps = <0x0>;
rxd0-skew-ps = <0x1a4>;
rxd1-skew-ps = <0x1a4>;
rxd2-skew-ps = <0x1a4>;
rxd3-skew-ps = <0x1a4>;
txen-skew-ps = <0x0>;
txc-skew-ps = <0x744>;
rxdv-skew-ps = <0x1a4>;
rxc-skew-ps = <0x690>;
max-frame-size = <0xed8>;
phandle = <0x24>;
};
ethernet@ff802000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
altr,sysmgr-syscon = <0x19 0x48 0x0>;
reg = <0xff802000 0x2000>;
interrupts = <0x0 0x5d 0x4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <0x100>;
snps,perfect-filter-entries = <0x80>;
tx-fifo-depth = <0x1000>;
rx-fifo-depth = <0x4000>;
clocks = <0x17>;
clock-names = "stmmaceth";
resets = <0x1a 0x21>;
reset-names = "stmmaceth";
snps,axi-config = <0x1b>;
status = "disabled";
phandle = <0x3b>;
};
ethernet@ff804000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
altr,sysmgr-syscon = <0x19 0x4c 0x0>;
reg = <0xff804000 0x2000>;
interrupts = <0x0 0x5e 0x4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <0x100>;
snps,perfect-filter-entries = <0x80>;
tx-fifo-depth = <0x1000>;
rx-fifo-depth = <0x4000>;
clocks = <0x17>;
clock-names = "stmmaceth";
snps,axi-config = <0x1b>;
status = "disabled";
phandle = <0x3c>;
};
gpio@ffc02900 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc02900 0x100>;
status = "disabled";
phandle = <0x3d>;
gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <0x2>;
snps,nr-gpios = <0x1d>;
reg = <0x0>;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupts = <0x0 0x70 0x4>;
phandle = <0x3e>;
};
};
gpio@ffc02a00 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc02a00 0x100>;
status = "okay";
phandle = <0x3f>;
gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <0x2>;
snps,nr-gpios = <0x1d>;
reg = <0x0>;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupts = <0x0 0x71 0x4>;
phandle = <0x1f>;
};
};
gpio@ffc02b00 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc02b00 0x100>;
status = "disabled";
phandle = <0x40>;
gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <0x2>;
snps,nr-gpios = <0x1b>;
reg = <0x0>;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupts = <0x0 0x72 0x4>;
phandle = <0x41>;
};
};
fpga-mgr@ffd03000 {
compatible = "altr,socfpga-a10-fpga-mgr";
reg = <0xffd03000 0x100 0xffcfe400 0x20>;
clocks = <0x17>;
resets = <0x1a 0x83>;
reset-names = "fpgamgr";
phandle = <0x4>;
};
i2c@ffc02200 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,designware-i2c";
reg = <0xffc02200 0x100>;
interrupts = <0x0 0x69 0x4>;
clocks = <0x1c>;
status = "okay";
phandle = <0x42>;
ds1339@68 {
compatible = "dallas,ds1339", "mxim,ds1339";
reg = <0x68>;
trickle-resistor-ohms = <0xfa>;
trickle-diode-disable;
};
};
i2c@ffc02300 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,designware-i2c";
reg = <0xffc02300 0x100>;
interrupts = <0x0 0x6a 0x4>;
clocks = <0x1c>;
status = "disabled";
clock-frequency = <0x186a0>;
i2c-sda-falling-time-ns = <0x1770>;
i2c-scl-falling-time-ns = <0x1770>;
phandle = <0x43>;
};
i2c@ffc02400 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,designware-i2c";
reg = <0xffc02400 0x100>;
interrupts = <0x0 0x6b 0x4>;
clocks = <0x1c>;
status = "disabled";
phandle = <0x45>;
};
i2c@ffc02500 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,designware-i2c";
reg = <0xffc02500 0x100>;
interrupts = <0x0 0x6c 0x4>;
clocks = <0x1c>;
status = "disabled";
phandle = <0x46>;
};
i2c@ffc02600 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,designware-i2c";
reg = <0xffc02600 0x100>;
interrupts = <0x0 0x6d 0x4>;
clocks = <0x1c>;
status = "disabled";
phandle = <0x47>;
};
spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xffda4000 0x100>;
interrupts = <0x0 0x65 0x4>;
num-cs = <0x4>;
clocks = <0x1d>;
status = "disabled";
phandle = <0x48>;
};
spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xffda5000 0x100>;
interrupts = <0x0 0x66 0x4>;
num-cs = <0x4>;
tx-dma-channel = <0x1e 0x10>;
rx-dma-channel = <0x1e 0x11>;
clocks = <0x1d>;
status = "disabled";
phandle = <0x49>;
};
sdr@ffcfb100 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffcfb100 0x80>;
phandle = <0x23>;
};
l2-cache@fffff000 {
compatible = "arm,pl310-cache";
reg = <0xfffff000 0x1000>;
interrupts = <0x0 0x12 0x4>;
cache-unified;
cache-level = <0x2>;
prefetch-data = <0x1>;
prefetch-instr = <0x1>;
arm,shared-override;
phandle = <0x1>;
};
dwmmc0@ff808000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "altr,socfpga-dw-mshc";
reg = <0xff808000 0x1000>;
interrupts = <0x0 0x62 0x4>;
fifo-depth = <0x400>;
clocks = <0x17 0x20>;
clock-names = "biu", "ciu";
status = "okay";
cap-sd-highspeed;
cap-mmc-highspeed;
broken-cd;
bus-width = <0x4>;
phandle = <0x26>;
};
nand@ffb90000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "altr,socfpga-denali-nand";
reg = <0xffb90000 0x72000 0xffb80000 0x10000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0x0 0x63 0x4>;
clocks = <0x21 0x18 0x22>;
clock-names = "nand", "nand_x", "ecc";
status = "disabled";
phandle = <0x4b>;
};
sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x40000>;
phandle = <0x4c>;
};
eccmgr {
compatible = "altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <0x19>;
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupts = <0x0 0x2 0x4 0x0 0x0 0x4>;
interrupt-controller;
#interrupt-cells = <0x2>;
ranges;
phandle = <0x4d>;
sdramedac {
compatible = "altr,sdram-edac-a10";
altr,sdr-syscon = <0x23>;
interrupts = <0x11 0x4 0x31 0x4>;
};
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
interrupts = <0x0 0x4 0x20 0x4>;
};
ocram-ecc@ff8c3000 {
compatible = "altr,socfpga-a10-ocram-ecc";
reg = <0xff8c3000 0x400>;
interrupts = <0x1 0x4 0x21 0x4>;
};
emac0-rx-ecc@ff8c0800 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0800 0x400>;
altr,ecc-parent = <0x24>;
interrupts = <0x4 0x4 0x24 0x4>;
};
emac0-tx-ecc@ff8c0c00 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0c00 0x400>;
altr,ecc-parent = <0x24>;
interrupts = <0x5 0x4 0x25 0x4>;
};
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
altr,ecc-parent = <0x1e>;
interrupts = <0xa 0x4 0x2a 0x4>;
};
usb0-ecc@ff8c8800 {
compatible = "altr,socfpga-usb-ecc";
reg = <0xff8c8800 0x400>;
altr,ecc-parent = <0x25>;
interrupts = <0x2 0x4 0x22 0x4>;
};
sdmmca-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <0x26>;
interrupts = <0xf 0x4 0x2f 0x4 0x10 0x4 0x30 0x4>;
};
};
spi@ff809000 {
compatible = "cdns,qspi-nor";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xff809000 0x100 0xffa00000 0x100000>;
interrupts = <0x0 0x64 0x4>;
cdns,fifo-depth = <0x80>;
cdns,fifo-width = <0x4>;
cdns,trigger-address = <0x0>;
clocks = <0x27>;
status = "disabled";
phandle = <0x4e>;
};
rstmgr@ffd05000 {
#reset-cells = <0x1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x100>;
altr,modrst-offset = <0x20>;
phandle = <0x1a>;
};
snoop-control-unit@ffffc000 {
compatible = "arm,cortex-a9-scu";
reg = <0xffffc000 0x100>;
phandle = <0x4f>;
};
sysmgr@ffd06000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd06000 0x300>;
cpu1-start-addr = <0xffd06230>;
phandle = <0x19>;
};
timer@ffffc600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xffffc600 0x100>;
interrupts = <0x1 0xd 0xf01>;
clocks = <0x28>;
};
timer0@ffc02700 {
compatible = "snps,dw-apb-timer";
interrupts = <0x0 0x73 0x4>;
reg = <0xffc02700 0x100>;
clocks = <0x1c>;
clock-names = "timer";
resets = <0x1a 0x44>;
reset-names = "timer";
phandle = <0x50>;
};
timer1@ffc02800 {
compatible = "snps,dw-apb-timer";
interrupts = <0x0 0x74 0x4>;
reg = <0xffc02800 0x100>;
clocks = <0x1c>;
clock-names = "timer";
resets = <0x1a 0x45>;
reset-names = "timer";
phandle = <0x51>;
};
timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0x0 0x75 0x4>;
reg = <0xffd00000 0x100>;
clocks = <0x29>;
clock-names = "timer";
resets = <0x1a 0x42>;
reset-names = "timer";
phandle = <0x52>;
};
timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0x0 0x76 0x4>;
reg = <0xffd01000 0x100>;
clocks = <0x29>;
clock-names = "timer";
resets = <0x1a 0x43>;
reset-names = "timer";
phandle = <0x53>;
};
serial0@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x100>;
interrupts = <0x0 0x6e 0x4>;
reg-shift = <0x2>;
reg-io-width = <0x4>;
clocks = <0x1c>;
status = "disabled";
phandle = <0x54>;
};
serial1@ffc02100 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02100 0x100>;
interrupts = <0x0 0x6f 0x4>;
reg-shift = <0x2>;
reg-io-width = <0x4>;
clocks = <0x1c>;
status = "okay";
phandle = <0x55>;
};
usbphy {
#phy-cells = <0x0>;
compatible = "usb-nop-xceiv";
status = "okay";
phandle = <0x2b>;
};
usb@ffb00000 {
compatible = "snps,dwc2";
reg = <0xffb00000 0xffff>;
interrupts = <0x0 0x5f 0x4>;
clocks = <0x2a>;
clock-names = "otg";
resets = <0x1a 0x23>;
reset-names = "dwc2";
phys = <0x2b>;
phy-names = "usb2-phy";
status = "okay";
disable-over-current;
phandle = <0x25>;
};
usb@ffb40000 {
compatible = "snps,dwc2";
reg = <0xffb40000 0xffff>;
interrupts = <0x0 0x60 0x4>;
clocks = <0x2a>;
clock-names = "otg";
resets = <0x1a 0x24>;
reset-names = "dwc2";
phys = <0x2b>;
phy-names = "usb2-phy";
status = "disabled";
phandle = <0x56>;
};
watchdog@ffd00200 {
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0x0 0x77 0x4>;
clocks = <0x29>;
status = "disabled";
phandle = <0x57>;
};
watchdog@ffd00300 {
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0x0 0x78 0x4>;
clocks = <0x29>;
status = "okay";
phandle = <0x58>;
};
};
aliases {
ethernet0 = "/soc/ethernet@ff800000";
serial0 = "/soc/serial1@ffc02100";
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
cff-file = "socfpga.periph.rbf";
early-release-fpga-config;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
};
a10leds {
compatible = "gpio-leds";
led0 {
label = "hps_led0";
gpios = <0x41 0x1 0x1>;
linux,default-trigger = "heartbeat";
default-state = "on";
};
};
gpio-keys {
compatible = "gpio-keys";
key0 {
label = "hps_key0";
linux,code = <0x67>;
gpios = <0x41 0x4 0x1>;
};
};
__symbols__ {
intc = "/intc@ffffd000";
pdma = "/soc/amba/pdma@ffda1000";
cb_intosc_hs_div2_clk = "/soc/clkmgr@ffd04000/clocks/cb_intosc_hs_div2_clk";
cb_intosc_ls_clk = "/soc/clkmgr@ffd04000/clocks/cb_intosc_ls_clk";
f2s_free_clk = "/soc/clkmgr@ffd04000/clocks/f2s_free_clk";
osc1 = "/soc/clkmgr@ffd04000/clocks/osc1";
main_pll = "/soc/clkmgr@ffd04000/clocks/main_pll@40";
main_mpu_base_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_mpu_base_clk";
main_noc_base_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_noc_base_clk";
main_emaca_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_emaca_clk@68";
main_emacb_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_emacb_clk@6c";
main_emac_ptp_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_emac_ptp_clk@70";
main_gpio_db_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_gpio_db_clk@74";
main_sdmmc_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_sdmmc_clk@78";
main_s2f_usr0_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_s2f_usr0_clk@7c";
main_s2f_usr1_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_s2f_usr1_clk@80";
main_hmc_pll_ref_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_hmc_pll_ref_clk@84";
main_periph_ref_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_periph_ref_clk@9c";
periph_pll = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0";
peri_mpu_base_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_mpu_base_clk";
peri_noc_base_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_noc_base_clk";
peri_emaca_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_emaca_clk@e8";
peri_emacb_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_emacb_clk@ec";
peri_emac_ptp_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_emac_ptp_clk@f0";
peri_gpio_db_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_gpio_db_clk@f4";
peri_sdmmc_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_sdmmc_clk@f8";
peri_s2f_usr0_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_s2f_usr0_clk@fc";
peri_s2f_usr1_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_s2f_usr1_clk@100";
peri_hmc_pll_ref_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@c0/peri_hmc_pll_ref_clk@104";
mpu_free_clk = "/soc/clkmgr@ffd04000/clocks/mpu_free_clk@60";
noc_free_clk = "/soc/clkmgr@ffd04000/clocks/noc_free_clk@64";
s2f_user1_free_clk = "/soc/clkmgr@ffd04000/clocks/s2f_user1_free_clk@104";
sdmmc_free_clk = "/soc/clkmgr@ffd04000/clocks/sdmmc_free_clk@f8";
l4_sys_free_clk = "/soc/clkmgr@ffd04000/clocks/l4_sys_free_clk";
l4_main_clk = "/soc/clkmgr@ffd04000/clocks/l4_main_clk";
l4_mp_clk = "/soc/clkmgr@ffd04000/clocks/l4_mp_clk";
l4_sp_clk = "/soc/clkmgr@ffd04000/clocks/l4_sp_clk";
mpu_periph_clk = "/soc/clkmgr@ffd04000/clocks/mpu_periph_clk";
sdmmc_clk = "/soc/clkmgr@ffd04000/clocks/sdmmc_clk";
qspi_clk = "/soc/clkmgr@ffd04000/clocks/qspi_clk";
nand_x_clk = "/soc/clkmgr@ffd04000/clocks/nand_x_clk";
nand_ecc_clk = "/soc/clkmgr@ffd04000/clocks/nand_ecc_clk";
nand_clk = "/soc/clkmgr@ffd04000/clocks/nand_clk";
spi_m_clk = "/soc/clkmgr@ffd04000/clocks/spi_m_clk";
usb_clk = "/soc/clkmgr@ffd04000/clocks/usb_clk";
s2f_usr1_clk = "/soc/clkmgr@ffd04000/clocks/s2f_usr1_clk";
socfpga_axi_setup = "/soc/stmmac-axi-config";
gmac0 = "/soc/ethernet@ff800000";
gmac1 = "/soc/ethernet@ff802000";
gmac2 = "/soc/ethernet@ff804000";
gpio0 = "/soc/gpio@ffc02900";
porta = "/soc/gpio@ffc02900/gpio-controller@0";
gpio1 = "/soc/gpio@ffc02a00";
portb = "/soc/gpio@ffc02a00/gpio-controller@0";
gpio2 = "/soc/gpio@ffc02b00";
portc = "/soc/gpio@ffc02b00/gpio-controller@0";
fpga_mgr = "/soc/fpga-mgr@ffd03000";
i2c0 = "/soc/i2c@ffc02200";
i2c1 = "/soc/i2c@ffc02300";
lcd = "/soc/i2c@ffc02300/lcd@28";
i2c2 = "/soc/i2c@ffc02400";
i2c3 = "/soc/i2c@ffc02500";
i2c4 = "/soc/i2c@ffc02600";
spi0 = "/soc/spi@ffda4000";
spi1 = "/soc/spi@ffda5000";
a10sr_gpio = "/soc/spi@ffda5000/resource-manager@0/gpio-controller";
a10sr_rst = "/soc/spi@ffda5000/resource-manager@0/reset-controller";
sdr = "/soc/sdr@ffcfb100";
L2 = "/soc/l2-cache@fffff000";
mmc = "/soc/dwmmc0@ff808000";
nand = "/soc/nand@ffb90000";
ocram = "/soc/sram@ffe00000";
eccmgr = "/soc/eccmgr";
qspi = "/soc/spi@ff809000";
rst = "/soc/rstmgr@ffd05000";
scu = "/soc/snoop-control-unit@ffffc000";
sysmgr = "/soc/sysmgr@ffd06000";
timer0 = "/soc/timer0@ffc02700";
timer1 = "/soc/timer1@ffc02800";
timer2 = "/soc/timer2@ffd00000";
timer3 = "/soc/timer3@ffd00100";
uart0 = "/soc/serial0@ffc02000";
uart1 = "/soc/serial1@ffc02100";
usbphy0 = "/soc/usbphy";
usb0 = "/soc/usb@ffb00000";
usb1 = "/soc/usb@ffb40000";
watchdog0 = "/soc/watchdog@ffd00200";
watchdog1 = "/soc/watchdog@ffd00300";
};
};
The arria10_hps_bridges node and its child node NVDLA_IP_0 is not being shown in /proc/iomem.
Here is the output of cat /proc/iomem enter image description here
Can anyone look into it and let me know why is linux not recognizing the arria10_hps_bridges node.
Thanks in advance
3G/1G. Now I have changed it in menuconfig to2G/2Gand recompiled it. After that, I was able to insert the KMD (which we discussed in the other question) for Ip connected to hps_bridge without error and the device tree nodearria10_hps_bridgesalso appeared iniomemright after that. What I understood from this is that for a node in the device tree to recognized by the kernel, a kernel device driver for the node must running in the kernel. Please correct me if I am wrong. – Shahid Ullahcat /proc/iomembut after I insert the module NVDLA_IP node got listed in the output ofcat /proc/iomem. – Shahid Ullah