In all the SystemVerilog test benches I could find on the internet the generator class always generates a fixed amount of samples and sends them to the mailbox. Driver reads the mailbox and generates an appropriate sequence by manipulating interface signals
One such generator, taken from [1] (chapter 1.3, paragraph 4) and reduced to essentials, is for example this:
class generator;
rand transaction trans;
mailbox gen2driv;
int repeat_count;
function new(mailbox gen2driv);
this.gen2driv = gen2driv;
endfunction
task main();
repeat(repeat_count) begin
trans = new();
if( !trans.randomize() ) $fatal("Gen:: trans randomization failed");
gen2driv.put(trans);
end
endtask
endclass
This one generates repeat_count samples and sends them to the mailbox.
There are however situations, where user wants to generate infinite stream of data, because the testbench simulation is not terminated by a lack of input data, but rather by validation of a condition which happens somewhere in the future, at unknown time.
Extending the above example to replace repeat(repeat_count) begin by forever begin won't work. The simulator freezes in the loop as it tries to put infinite amount of samples to the mailbox. As the execution of main task is a blocking action, driver's signal generator never get executed, and the entire simulation stalls.
So my question is: How to define correctly a generator class, which can send infinite stream of data?
I'm looking for a behaviour similar to pythonic yield and generator function. This however requires some communication between driver and generator. So such generator model is probably not very suitable for SV?
[1] https://verificationguide.com/systemverilog-examples/systemverilog-testbench-example-01