I am making a traffic light controller using a moore circuit with a N/S light and and E/W light and my output keeps coming out as all X's

Question

Here are the parameters enter image description here

I have ran the files and checked the gtk wave and I can't figure out where my wiring is going wrong. I am using a moore circuit with one input. I just need someone to help me figure out where I am messing up the wiring. Thanks

module traffic(T, CLK, GN, YN, RN, GE, YE, RE);

// inputs
input CLK;
input T;

// outputs
output reg GN;
output reg YN;
output reg RN;
output reg GE;
output reg YE;
output reg RE;

// flip-flops 
reg gN = 1'b1;
reg yN = 1'b0;
reg rN = 1'b0;
reg gE = 1'b0;
reg yE = 1'b0;
reg rE = 1'b1;

// Wires
wire gNplus = 1'b1; 
wire yNplus = 1'b0; 
wire rNplus = 1'b0; 
wire gEplus = 1'b0;
wire yEplus = 1'b0;
wire rEplus = 1'b1;

// Next State and Output
assign CLK = 0;
always @(posedge CLK) 
begin
    gN <= gNplus;
    yN <= yNplus;
    rN <= rNplus;
    gE <= gEplus;
    yE <= yEplus;
    rE <= rEplus;

    GN <= gN;
    YN <= yN;
    RN <= rN;
    GE <= gE;
    YE <= yE;
    RE <= rE;

end 

// combinational logic
assign gNplus = ~T * ~yN;
assign yNplus = gN;
assign rNplus = (rN * T) | yN;
assign gEplus = ~T * ~yE;
assign yEplus = gE;
assign rEplus = (rE * T) | yE;

endmodule

Test bench include "traffic.v" timescale 10ns/1ns

module traffic_test;

reg T; 

wire GN;
wire YN;
wire RN; 
wire GE; 
wire YE;
wire RE;

traffic UUT(.T(T), .CLK(CLK), .GN(gNplus), .YN(yNplus), .RN(rNplus), .GE(gEplus), .YE(yEplus), .RE(rEplus));

reg CLK = 1'b1;
always  
begin
    CLK = ~CLK;
    #5;
end


initial begin
    T = 0;
    forever begin
        #20 T = ~T;
    end

end

initial begin
        $display("START OF TEST");
        $dumpfile("traffic.vcd");
        $dumpvars(0, traffic_test);
        
        $display("T | GN YN RN | GE YE RE");
    
        for (integer i = 0;i < 11;i =i + 1) 
        begin
            {T} = i;
            $display("%b |  %b  %b  %b |  %b  %b  %b", T, gNplus, yNplus, rNplus, gEplus, yEplus, rEplus);
        end
        $finish;
        $display("END OF TEST");
    end

endmodule

Serge Serge · Accepted Answer · 2021-04-19T15:00:40

You code does not have proper reset and multiple drivers on your wires.

The following statement is not a simple initialization statement.

wire gNplus = 1'b1; 
wire yNplus = 1'b0; 
...

Those statements are same as

wire gNplus;
assign gNplus = 1'b1; 
wire yNplus;
assign yNplus = 1'b0;

Now you have another set of statements:

assign gNplus = ~T * ~yN;
assign yNplus = gN;
...

You are driving the same wires twice with different values. The resulting value will be X.

The following is not necessarily a proper initialization of the register. First of all it is not always synthesizable. Secondly it is done before time 0 of simulation and any side effects of initial simulation step can re-write them with wrong values. You should come up with a reset sequence for the flop.

reg gN = 1'b1;
reg yN = 1'b0;
...

A couple of other side notes.

What does this statement do in your code: assign CLK = 0;? You initialize your clock in test bench to 1. It would be better to do it in an initial block though.
you declare your CLK signal in the test bench after you use it. This way the verilog can use a default type, which usually is a wire.

I am making a traffic light controller using a moore circuit with a N/S light and and E/W light and my output keeps coming out as all X's

1 Answers