Minimum time between falling and rising edge to detect a rising edge on a GPIO on STM32H7

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votes

On my STM32H753 I've enabled an interruption on the rising edge of one of the GPIOs. Once I get the interrupt (provided of course that the handler acknowledges the IT in the EXTI peripheral), when the signal goes low again, I will be able to get another interruption at the following rising edge.

My question is: what is the minimal duration between the falling edge and the rising edge for the latter to be detected by EXTI ? The datasheet specifies many characteristics of the IOs, in particular the voltage values to consider the input low or high but I didn't find this timing.

Thank you

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iostm32interrupt
This is a bit of a guess so I'm putting it in a comment rather than as an answer: The GPIO input is sampled on the AHB clock. If you clear the interrupt flag on one AHB cycle I would expect the chosen edge to be detected if the state is present at the next AHB cycle. i.e: A pulse of infinitesimally small width could be detected if it coincides with the clock, a pulse longer than the AHB period is guaranteed to be detected. - Tom V

1 Answers

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For the electonic part, you need to refere to you MCU datasheet. However I beleive you need the information about the software part:

You will be able to handle a new GPIO IRQ (EXTI) as soon as you've aknowlegded the former one by clearing the IRQPending Flag or via HAL APIs.

If two IRQs occurred and you did not clear the IRQPending flag yet, then they will be considered as one IRQ. Benchamrking such delay depends on the Clock speed you're using and the complexity of your EXTI_IRQ_Handler routine.