How to automatically convert port signals of verilog sub modules using python?

Question

Let's say there is a TOP module, one logic (logic1) and one test logic (logic2) like in the left picture.

I want to exclude test logic like in the right picture (all verilog form).

At first, If we suppose all the logics (logic and test logic) are instantiated inside the TOP module,

The left side of verilog code would be something like this. (Let's say a-> blue, b-> yellow, c-> red, d-> green, signal b penetrates test logic)

module TOP (

input  a1,
input  b1,
input  c1,
output d1
);
wire   b2;
wire   c2;

logic1 U_logic(
.A (a1),
.B (b2),
.C (c2),
.D (d1),
);

logic2 U_testlogic(
.B    (b2),
.C_IN (c1),
.C    (c2),
);

endmodule

The right side of verilog code would be something like this.

module TOP (

input  a1,
input  b1,
input  c1,
output d1
);

logic1 U_logic(
.A (a1),
.B (b1),
.C (c1),
.D (d1),
);

endmodule

If the number of logics and test logics are more than 100, and it is hard to exclude all the test logic manually, How can I deal with this automatically by using Python code (The number of logics and test logics are same)?

The main goal is to convert port signal of test logic (logic2) to port signal of logic (logic1) and remove test logic. [ex. c2->c1 (.C port signal -> .C_IN port signal), b2->b1 (penetrating signal -> specific input), remove logic2]

Also your question is very broad and also missing details. According to what you show here, the answer is quite simple: parse U_logic's interface and change the ports x2 to x1. The question is what is the real criteria for replacement — Tomerikoo
No, but good point. actually I supposed b2 signal connected by other abbreviated instance(When actual TOP module). U can disregard about signal B then if that's gonna be a guestion though. — 진주형
As I mentioned and u also said, the criteria gonna be changing port signal * -> *_IN . and remove test logics. And I think u got the point but I found hard to parse it by using python. — 진주형
Again, your problem can be very easy, all depending on the perquisites. What I mean by that is if let's say all inputs are as your example a, b, etc. And the outputs from the test logic are pre/suffixed like let's say a_test, b_test, etc. then all you need to do is something like re.sub(r"(w+)_test", "\1", line) for each line of the interface — Tomerikoo

Tomerikoo Tomerikoo · Accepted Answer · 2021-02-02T13:35:19

An outline of a possible solution is as follows:

import re

with open("test.txt") as in_file, open("output.txt", 'w') as out_file:
    for line in in_file:
        if "U_logic" in line:
            out_file.write(line)
            for line in in_file:
                if ");" in line:
                    break
                out_file.write(re.sub(r"(\.\w+\s*\(\w+)2", r"\g<1>1", line))

        elif "U_testlogic" in line:
            for line in in_file:
                if ");" in line:
                    break

        else:
            out_file.write(line)

What this does is:

parse each line of the file.
Once the declaration of U_logic is encountered, start a new loop and:
- Write each line to the new file until reaching the );. The replacement itself is done by the regex shown which can be observed and modified in this demo.
Once the declaration of U_testlogic is reached, simply skip all lines until );.
All other lines are passed on without change to the new file.

This is just an outline because there might be many more cases to take in count:

What if there are parameters to the modules?
What if the ); is at the same line as the last port?
What if the whole instantiation is on one line?
etc. etc.

I will leave it to you to work-out those details.

How to automatically convert port signals of verilog sub modules using python?

1 Answers