AXI Verification IP Test Example

Question

I'm trying to setup Vivado AXI Verification IP as a slave agent that only receives write transactions.... What I get is an error that a packageis not found when I try to copy code from the example provided by vivado into my own project. see below.

ERROR: [VRFC 10-2989] 'ex_sim_axi_vip_slv_0_pkg' is not declared [C:/Users/vivado_hater/Documents/fpga/pcie_root/tb/tb_vip_ctrl.sv:4]
INFO: [VRFC 10-311] analyzing module tb_vip_ctrl

// Module to Control AXI Verification IP....

import axi_vip_pkg::*; 
import ex_sim_axi_vip_slv_0_pkg::*;

module tb_vip_ctrl #(parameter test_mode = 1);

    generate if (test_mode == 1) begin: init
      
        ex_sim_axi_vip_slv_0_slv_t     agent;
    
        initial begin
            agent = new(
                "slave vip agent",
                tb_top.axi_vip_0.inst.IF
            ); 
                
            agent.start_slave();
    
            fork
                wr_response();
            join_none
        end
    
        task wr_response();
            // Declare a handle for write response
            axi_transaction                    wr_reactive;  
        
            forever begin                                   
                // Block till write transaction occurs  
                agent.wr_driver.get_wr_reactive (wr_reactive); 
            
                // User fill in write response
                fill_wr_reactive                (wr_reactive); 
            
                // Write driver send response to VIP interface
                agent.wr_driver.send            (wr_reactive); 
            end
        endtask
      
        function automatic void fill_wr_reactive(inout axi_transaction t);
            t.set_bresp(XIL_AXI_RESP_OKAY);
        endfunction: fill_wr_reactive
    
    end endgenerate

endmodule

`timescale 1ns / 1ps

module tb_top ();
    // ...
    // Removed declarations...
    // ...

    axi_vip_0 axi_vip_0(
        .aclk           (m_axi_aclk),        
        .aresetn        (m_axi_aresetn),     
        
        .s_axi_awid     (m_axi_wa_id),       
        .s_axi_awaddr   (m_axi_wa_addr),     
        .s_axi_awlen    (m_axi_wa_len),      
        .s_axi_awsize   (m_axi_wa_size),     
        .s_axi_awburst  (m_axi_wa_burst),    
        .s_axi_awlock   (m_axi_wa_lock),     
        .s_axi_awcache  (m_axi_wa_cache),    
        .s_axi_awprot   (m_axi_wa_prot),     
        .s_axi_awvalid  (m_axi_wa_valid),    
        .s_axi_awready  (m_axi_wa_ready),    
        .s_axi_awregion (m_axi_wa_region),   
        .s_axi_awqos    (m_axi_wa_qos),      
        .s_axi_wdata    (m_axi_wd_data),     
        .s_axi_wstrb    (m_axi_wd_strb),     
        .s_axi_wlast    (m_axi_wd_last),     
        .s_axi_wvalid   (m_axi_wd_valid),    
        .s_axi_wready   (m_axi_wd_ready),    
        .s_axi_bid      (m_axi_wb_id),       
        .s_axi_bresp    (m_axi_wb_resp),     
        .s_axi_bvalid   (m_axi_wb_valid),    
        .s_axi_bready   (m_axi_wb_ready),    
        
        .s_axi_arid     (m_axi_ra_id),       
        .s_axi_araddr   (m_axi_ra_addr),     
        .s_axi_arlen    (m_axi_ra_len),      
        .s_axi_arsize   (m_axi_ra_size),     
        .s_axi_arburst  (m_axi_ra_burst),    
        .s_axi_arlock   (m_axi_ra_lock),     
        .s_axi_arcache  (m_axi_ra_cache),    
        .s_axi_arprot   (m_axi_ra_prot),     
        .s_axi_arvalid  (m_axi_ra_valid),    
        .s_axi_arready  (m_axi_ra_ready),    
        .s_axi_arregion (m_axi_ra_region),   
        .s_axi_arqos    (m_axi_ra_qos),      
        .s_axi_rid      (m_axi_rd_id),       
        .s_axi_rdata    (m_axi_rd_data),     
        .s_axi_rresp    (m_axi_rd_resp),     
        .s_axi_rlast    (m_axi_rd_last),     
        .s_axi_rvalid   (m_axi_rd_valid),    
        .s_axi_rready   (m_axi_rd_ready)     
    );
    
    tb_vip_ctrl tb_vip_ctrl();
    
endmodule

Bimo Bimo · Accepted Answer · 2020-09-24T17:37:58

// AXI VIP core from Xilinx/Vivado requires 
// you to import two packages into the SystemVerilog 
// testbench: 
// 
//      import axi_vip_pkg::*;
//      import "VIP_component_name"_pkg::*;
// 
// When you declare the agent in the verilog the 
// instantiation type comes from the package
// "VIP_component_name"_pkg and is declared as:
// 
//     "VIP_component_name"_slv_t  agent;
//

Example:

import axi_vip_pkg::*;
import axi_vip_0_pkg::*;

module tb_vip_ctrl #(parameter test_mode = 1);

    generate if (test_mode == 1) begin: init
      
        axi_vip_0_slv_t  agent;

        initial begin
            agent = new(
                "slave vip agent",
                tb_top.axi_vip_0.inst.IF
            ); 
                
            agent.start_slave();
    
            fork
                wr_response();
            join_none
        end
    
        task wr_response();
            // Declare a handle for write response
            axi_transaction                    wr_reactive;  
        
            forever begin                                   
                // Block till write transaction occurs  
                agent.wr_driver.get_wr_reactive (wr_reactive); 
            
                // User fill in write response
                fill_wr_reactive                (wr_reactive); 
            
                // Write driver send response to VIP interface
                agent.wr_driver.send            (wr_reactive); 
            end
        endtask
      
        function automatic void fill_wr_reactive(inout axi_transaction t);
            t.set_bresp(XIL_AXI_RESP_OKAY);
        endfunction: fill_wr_reactive
    
    end endgenerate

endmodule

AXI Verification IP Test Example

1 Answers