It appears that most/all of the Data
types in Chisel are sealed classes which do not allow a user to extend from them. Is it possible to add information regarding some user defined fields or to add support in the future?
I think there are a few cases where it could be helpful to have additional information:
Port descriptions possibly for documentation
Voltage levels/biases
- If you are doing some chip top level connections you may have to make certain connection
- Also many times signals will have a
set_dont_touch
(an SDC, not to be confused with ChiseldontTouch
) placed on them, so it may be possible to add these for auto SDC constraints.
Modeling purposes
- Chisel obviously doesn't deal with behavioral modeling, but there are times where a Verilog/SV
real
is used for modeling. This could be used to print out where these signals are for any post processing.
- Chisel obviously doesn't deal with behavioral modeling, but there are times where a Verilog/SV
I don't expect Chisel to handle all of the actual cases (such as making the document or dealing with connections), but if these members can be added/extended a user can either check these during construction and/or after elaboration for additional flows.
Thanks