Error: syntax error in set_input_delay (Quartus)

Question

The Fmax parameter in my code was reported as : No Paths to report. Therefore, I was trying to set input signal relationship with the defined clock using set_input_delay. However, the error report states:

Verilog HDL Syntax error near text "-" ; expecting "." or "(".

I checked the documentation on the Intel website, and it shows that the correct syntax is:

set_input_delay -clock clk 1.5 [get_ports myin]

module DT2(a,b,c,f,e,g,newin,v,w,x,m,n,F1,r,N1,D1,p,q,j,n1,t,clk,new);

input clk;
input [10:0]new;

set_input_delay -clock clk 1.5 [get_ports new];

output reg [12:0]a;
output reg [11:0]b;
output reg [10:0]c,f,e,g,m,n,F1,r;
output reg [10:0]newin;
output reg [40:0]v;
output reg [30:0]w;
output reg [20:0]x,N1,D1,p,q,n1;
output reg [1:0]j;
output reg t;
integer i;




initial
begin
a=13'b100_1000011111; //3.10
b=12'b10_1110011110; // 2.10
c=11'b1_0000101010; //1.10

e=11'b0_0000100100; //1.10
f=11'b0_0010111100; //1.10
g=11'b0_0111000000; //1.10
end

always @ (posedge clk)
begin
newin=new;
t=newin[10];
if(t==1'b1)
begin
newin=newin-11'b1_0000000000;
v = (newin*newin*newin*e);
w = (newin*newin*f); 
x = (newin*g);
m=(v[40:30])+(x[20:10])+(11'b0_0000000101);
n = m-(w[30:20]);
x=(n*n);
n=n<<1;
m=n-x[20:10];  //need to keep
n=n>>1;
n=(11'b1_0000000000)-n;
end

else
begin
v = (newin*newin*newin*a);
w = (newin*newin*b);
x = (newin*c);

m=(v[40:30])+(x[20:10])+(11'b0_0000001100);
n = m-(w[30:20]);
x=(n*n);
n=n<<1;
m=n+x[20:10];  //need to keep
n=n>>1;
n=(11'b1_0000000000)+n;

end


n1=(n*n);
//SHIFTING NONE

j=2'b00;
for(i=0;i<=16;i=i+1)
    begin
    if(j==2'b00)
        begin
        N1=m*(n1[20:10]);
        D1=(n1[20:10])*(n1[20:10]);
        F1=12'b10_0000000000-D1[20:10];
        j=2'b01;
        end
    else if(j==2'b01)
        begin
        p=F1*N1[20:10];
        q=F1*D1[20:10];
        r=12'b10_0000000000-D1[20:10];
        j=2'b10;
        end
    else if(j==2'b10)
        begin
        N1=r*p[20:10];
        D1=r*q[20:10];
        F1=12'b10_0000000000-D1[20:10];
        j=2'b01;
        end
        
    end

end


endmodule

toolic toolic · Accepted Answer · 2020-08-08T14:24:50

You must remove the following line from your Verilog code because it is not legal Verilog syntax:

set_input_delay -clock clk 1.5 [get_ports new];

It looks like a command for your synthesis tool, and it likely belongs in a synthesis script.

Error: syntax error in set_input_delay (Quartus)

2 Answers