Synthesis for statements of wait, infinite loop, while loop, and for loop in VHDL

0
votes

I hardly use any loops in Verilog for the synthesis purpose except "for" loops on the initialization of memories.

In VHDL, it is advised that wait statement usage should be limited in synthesis. Then, under what conditions that the wait statement usage can be synthesized? How about other loop statements, such as infinite loop ([loop_label]LOOP ... END LOOP), while loop, and for loop?

1
loopsvhdlwaitsynthesis
Not all VHDL constructs are synthesisable, but all are useful in simulation. - Tricky
See IEEE Std 1076.6-2004, IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis (withdrawn) 6. Modeling hardware elements, 8. Syntax, 8.8.1 Wait statement, 6.1.3.2 Edge-sensitive storage using a single wait statement and 6.1.3.4 Edge-sensitive storage with multiple waits, 8.8.9 Loop statement, Every VHDL synthesis tool will adhere with varying degrees of compliance to this lapsed standard. - user1155120

1 Answers

0
votes

You can use a loop to iterate over arrays or vectors. Wait statements are not synthesizable and are only used for simulation. Usually wait a x amount of time or wait until y happens is done by implementing counters and/or a state machine. Infinite loops cannot work as you would need an infinitely big chip to create the hardware.