What are the use of rand_mode(val)?

Question

according to uvm_users_guide_1.1, page 152, these 2 implementations are shown: First:

class my_seq extends uvm_sequence #(my_item);
... // Constructor and UVM automation macros go here.
    // See Section 4.8.2
virtual task body();
 `uvm_create(req)
 req.addr.rand_mode(0); // Disables randomization of addr
 req.dc1.constraint_mode(0); // Disables constraint dc1
 req.addr = 27;
 ...
endtask : body
endclass: my_seq

and:

class my_seq2 extends uvm_sequence #(my_item);
... // Constructor and UVM automation macros go here.
    // See Section 4.8.2
virtual task body();
`uvm_create(req)
req.addr = 27;
req.data = 4;
// No randomization. Use a purely pre-generated item.
`uvm_send(req)
endtask : body
endclass: my_seq2

What will be the difference if I`ll not use the "rand_mode(0)" and "constraint_mode(0)" as in the second example?

Answer 1

rand_mode(0) is feature of SystemVerilog that the UVM example is using to freeze a random variable like it was a non-rand variable when calling randomize(). You usually do this when you need to fix one random variable to a particular value, but want others to be randomized as usual.

The second example shows how you can set all the random variables without ever calling randomize(). Many people forget (especially if they are coming from another language e) that when doing constrained random verification that you don't always have to call randomize(). They'll go out of their way to add constraints like

req.randomize() with { addr == 27; data == 4; } when it would have been easier to just to do it as the second example shows.

See sections 18.8 and 18.7 of the IEEE 1800-2017 SystemVerilog LRM.

Answer 2

The user guide gives you a hint:

NOTE — You might need to disable a constraint to avoid a conflict.

In my_seq, there could be a difference if you call randomize(). Consider this scenario:

rand bit [5:0] addr;
rand bit [7:0] data;
constraint dc1 { data==addr; data != 27; }

randomize will fail if you disable randomization of addr, set addr=27 and don't disable the dc1 constraint.